External Match Register (Emr, Timer0: T0Emr - 0Xe000 403C; And Timer1: T1Emr - 0Xe000 803C); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 170: Capture Control Register (CCR, TIMER0: T0CCR - address 0xE000 4028 and TIMER1: T1CCR - address
0xE000 8028) bit description
Bit Symbol Value Description
10 CAP3FE 1
0
11 CAP3I 1
0
15:12 -
[1]
15.5.11 External Match Register (EMR, TIMER0: T0EMR - 0xE000 403C; and
TIMER1: T1EMR - 0xE000 803C)
The External Match Register provides both control and status of the external match pins
MAT(0-3).
If the match ouputs are configured as PWM output, the function of the external match
registers is determined by the PWM rules
controlled PWM ouputs" on page
Table 171: External Match Register (EMR, TIMER0: T0EMR - address 0xE000 403C and TIMER1: T1EMR -
address0xE000 803C) bit description
Bit Symbol Description
0 EM0 External Match 0. This bit reflects the state of output MAT0.0/MAT1.0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the
functionality of this output.
1 EM1 External Match 1. This bit reflects the state of output MAT0.1/MAT1.1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the
functionality of this output.
2 EM2 External Match 2. This bit reflects the state of output MAT0.2/MAT1.2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output.
3 EM3 External Match 3. This bit reflects the state of output MAT0.3/MAT1.3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this output
of the timer can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control
the functionality of this output.
5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0.
shows the encoding of these bits.
7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1.
shows the encoding of these bits.

User manual

Capture on CAPn.3 falling edge: a sequence of 1 then 0 on CAPn.3 will cause CR3 to
be loaded with the contents of TC
This feature is disabled.
Interrupt on CAPn.3 event: a CR3 load due to a CAPn.3 event will generate an
[1]
interrupt .
This feature is disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
On Timer0, CAP0.3 is disabled and values for CAP3RE, CAP3FE, and CAP3I are not defined.
Rev. 01 — 12 January 2006
[1]
.
(Section 15.5.13 "Rules for single edge
197).
UM10161
Chapter 15: Timer0 and Timer1
Table 172
Table 172
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
0
NA
Reset
value
0
0
0
0
00
00
195