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10.1 Features
10.2 Pin description
Table 97:
UART1 pin description
Pin
Type
Description
RXD1
Input
Serial Input. Serial receive data.
TXD1
Output
Serial Output. Serial transmit data.
CTS1
Input
Clear To Send. Active LOW signal indicates if the external modem is ready to accept transmitted
data via TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the
complement value of this signal is stored in U1MSR[4]. State change information is stored in
U1MSR[0] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
DCD1
Input
Data Carrier Detect. Active LOW signal indicates if the external modem has established a
communication link with the UART1 and data may be exchanged. In normal operation of the
modem interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State
change information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled
(U1IER[3] = 1).
DSR1
Input
Data Set Ready. Active LOW signal indicates if the external modem is ready to establish a
communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0),
the complement value of this signal is stored in U1MSR[5]. State change information is stored in
U1MSR[1] and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
DTR1
Output
Data Terminal Ready. Active LOW signal indicates that the UART1 is ready to establish connection
with external modem. The complement value of this signal is stored in U1MCR[0].
RI1
Input
Ring Indicator. Active LOW signal indicates that a telephone ringing signal has been detected by
the modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of
this signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source
for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
RTS1
Output
Request To Send. Active LOW signal indicates that the UART1 would like to transmit data to the
external modem. The complement value of this signal is stored in U1MCR[1].
10.3 Register description
UART1 contains registers organized as shown in Table 76. The Divisor Latch Access Bit
(DLAB) is contained in U1LCR[7] and enables access to the Divisor Latches.
User manual
UM10161
Chapter 10: Universal Asynchronous Receiver/Transmitter 1
(UART1)
Rev. 01 — 12 January 2006
•
UART1 is identical to UART0 with the addition of a modem interface.
•
UART1 contains 16 byte Receive and Transmit FIFOs.
•
Register locations conform to '550 industry standard.
•
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
•
Fractional baud rate generator with autobauding capabilities is built-in.
•
Mechanism enables software and hardware flow control implementation.
•
Standard modem interface signals are included, and flow control (auto-CTS/RTS) is
fully supported in hardware.
Rev. 01 — 12 January 2006
User manual
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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