Block Diagram - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

1.9 Block diagram

LPC2101/2102/2103
HIGH SPEED
P0[31:0]
GENERAL
PURPOSE I/O
INTERNAL
SRAM
CONTROLLER
2 kB/4 kB/
8 kB SRAM
EINT2 to
(1)
EINT0
3 × CAP0
(1)
4 × CAP1 (1)
3 × CAP2
(1)
3 × MAT0 (1)
4 × MAT1 (1)
3 × MAT2
(1)
4 × MAT3 (1)
AD0[7:0]
P0[31:0]
(1) Pins shared with GPIO.
Fig 1. LPC2101/02/03 block diagram
User manual
TRST
8 kB
BOOT ROM
ARM7 local bus
MEMORY
ACCELERATOR
8 kB/16 kB/
32 kB FLASH
EXTERNAL
INTERRUPTS
CAPTURE/COMPARE
EXTERNAL COUNTER
TIMER 0/TIMER 1/
TIMER 2/TIMER 3
ADC
GENERAL
PURPOSE I/O
WATCHDOG
TIMER
Rev. 01 — 12 January 2006
TMS TDI
TCK TDO
TEST/DEBUG
INTERFACE
PLL
ARM7TDMI-S
system
AHB BRIDGE
clock
AMBA AHB
(Advanced High-performance Bus)
AHB TO APB
BRIDGE
APB (ARM
peripheral bus)
I
INTERFACES 0 AND 1
SERIAL INTERFACES
REAL-TIME CLOCK
SYSTEM CONTROL
UM10161
Chapter 1: Introductory information
XTAL2 V V
DD(3V3) DD(1V8)
XTAL1 RST V
SS
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
2
C-BUS SERIAL
SPI AND SSP
UART0/UART1
002aab814
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
(1)
SCL0, SCL1
(1)
SDA0, SDA1
(1)
SCK0, SCK1
(1)
MOSI0, MOSI1
(1)
MISO0, MISO1
(1)
SSEL0, SSEL1
(1)
TXD0, TXD1
(1)
RXD0, RXD1
DSR1, CTS1,
RTS1, DTR1
DCD1, RI1
RTXC1
RTXC2
VBAT
7