Phase Locked Loop (Pll); Register Description - Philips LPC2101 User Manual

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For example, whenever a Software Interrupt request is generated, the ARM core will
always fetch 32-bit data "residing" on 0x0000 0008 see
locations" on page
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000 0008 will provide data
available also at 0x7FFF E008 (Boot Block remapped from on-chip Bootloader).

3.8 Phase Locked Loop (PLL)

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The
input frequency is multiplied up the range of 10 MHz to 60 MHz using a Current Controlled
Oscillators (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on the LPC2104/05/06 due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is
shown in
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values
are controlled by the PLLCFG register. These two registers are protected in order to
prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip
operations, including the watchdog timer, are dependent on the PLL when it is providing
the chip clock, accidental changes to the PLL setup could result in unexpected behavior of
the microcontroller. The protection is accomplished by a feed sequence similar to that of
the watchdog timer. Details are provided in the description of the PLLFEED register.
The PLL is turned off and bypassed following a chip Reset and when by entering
Power-down mode. The PLL is enabled by software only. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

3.8.1 Register description

The PLL is controlled by the registers shown in
follow.
Warning: Improper setting of the PLL values may result in incorrect operation of the
device!
User manual
12. This means that when MEMMAP[1:0]=10 (User RAM Mode), a
Figure 9.
Rev. 01 — 12 January 2006
UM10161
Chapter 3: System control block
Table 3 "ARM exception vector
Table 15. More detailed descriptions
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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