User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

User manual

feed sequence
feed error
feed ok
WDFEED
PLCK
WDTV
register
(1) Counter is enabled only when the WDEN bit is set and a valid feed sequence is done.
(2) WDEN and WDRESET are sticky bits. Once set they can't be cleared until the watchdog
underflows or an external reset occurs.
Fig 60. Watchdog block diagram
Rev. 01 — 12 January 2006
WDTC
32 BIT DOWN
/ 4
COUNTER
CURRENT WD
TIMER COUNT
WDMOD
2
WDEN WDTOF
register
UM10161
Chapter 18: WDT
underflow
enable
1
count
SHADOW BIT
WDINT WDRESET
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
reset
interrupt
228