Pwm Control Register (Pwmcon, Timer0: Pwm0Con - 0Xe007 0074 And Timer1: Pwm1Con - 0Xe007 4074); Ouputs; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
16.6 PWM Control register (PWMCON, TIMER0: PWM0CON - 0xE007 0074
and TIMER1: PWM1CON - 0xE007 4074)
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three single edge controlled PWM outputs can be selected
on the MATn.2:0 outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM outputs are cleared.
Table 183: PWM Control Register (PWMCON, TIMER0: PWM0CON - 0xE007 0074 and
Bit
0
1
1
1
4:32
16.7 Rules for single edge controlled PWM ouputs

User manual

TIMER1: PWM1CON - 0xE007 4074) bit description
Symbol Description
PWM enable When one, PWM mode is enabled for MATn.0. When
zero, MATn.0 is controlled by EM0.
PWM enable When one, PWM mode is enabled for MATn.1. When
zero, MATn.1 is controlled by EM1.
PWM enable When one, PWM mode is enabled for MATn.2. When
zero, MATn.2 is controlled by EM2.
PWM enable When one, PWM mode is enabled for MATn.3. When
zero, MATn.3 is controlled by EM3.
Note: It is recommended to use MATn.3 to set the PWM
cycle because it is not pinned out on Timer0.
- Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
(timer is set to zero) unless their match value is equal to zero.
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
3. If a match value larger than the PWM cycle length is written to the match register, and
the PWM signal is HIGH already, then the PWM signal will be cleared on the next
timer reset.
4. If a match register contains the same value as the timer reset value (the PWM cycle
length), then the PWM output will be reset to LOW on the next clock tick. Therefore,
the PWM output will always consist of a one clock tick wide positive pulse with a
period determined by the PWM cycle length (i.e. the timer reload value).
5. If a match register is set to zero, then the PWM output will go to HIGH at the first time
the timer reaches its reset value and will stay HIGH continuously.
Rev. 01 — 12 January 2006
UM10161
Chapter 16: Timer2 and Timer3
Reset value
0
0
0
0
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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