Timer Counter (Tc, Timer2: T2Tc - 0Xe007 0008 And Timer3: T3Tc - 0Xe007 4008); Prescale Register (Pr, Timer2: T2Pr - 0Xe007 000C And Timer3: T3Pr - 0Xe007 400C); Prescale Counter Register (Pc, Timer2: T2Pc - 0Xe007 0010 And Timer3: T3Pc - 0Xe007 4010); Match Registers (Mr0 - Mr3) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 178: Count Control Register (CTCR, TIMER2: T2CTCR - address 0xE007 0070 and
Bit
3:2
7:4
16.5.4 Timer Counter (TC, TIMER2: T2TC - 0xE007 0008 and TIMER3:
T3TC - 0xE007 4008)
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0xE000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
16.5.5 Prescale Register (PR, TIMER2: T2PR - 0xE007 000C and TIMER3:
T3PR - 0xE007 400C)
The 16-bit Prescale Register specifies the maximum value for the Prescale Counter.
16.5.6 Prescale Counter register (PC, TIMER2: T2PC - 0xE007 0010 and
TIMER3: T3PC - 0xE007 4010)
The 16-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the
resolution of the timer and the maximum time before the timer overflows. The Prescale
Counter is incremented on every PCLK. When it reaches the value stored in the Prescale
Register, the Timer Counter is incremented, and the Prescale Counter is reset on the next
PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs
when PR = 1, etc.

16.5.7 Match Registers (MR0 - MR3)

The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.

User manual

TIMER3: T3TCR - address 0xE007 4070) bit description
Symbol Value Description
Count When bits 1:0 in this register are not 00, these bits select
Input which CAP pin is sampled for clocking:
Select
00 CAP2.0
01 CAP2.1
10 CAP2.2
Note: If Counter mode is selected for a particular CAPn input
in the TnCTCR, the 3 bits for that input in the Capture Control
Register (TnCCR) must be programmed as 000. However,
capture and/or interrupt can be selected for the other 3 CAPn
inputs in the same timer.
- CAPn.3 are not available on Timer2/3
- - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 16: Timer2 and Timer3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
00
NA
205