Timer Counter (Tc, Timer0: T0Tc - 0Xe000 4008 And Timer1: T1Tc - 0Xe000 8008); Prescale Register (Pr, Timer0: T0Pr - 0Xe000 400C And Timer1: T1Pr - 0Xe000 800C); Count Control Register; Prescale Counter Register (Pc, Timer0: T0Pc - 0Xe000 4010 And Timer1: T1Pc - 0Xe000 8010) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 168: Count Control Register (CTCR, TIMER0: T0CTCR - address 0xE000 4070 and
Bit
3:2
7:4
15.5.4 Timer Counter (TC, TIMER0: T0TC - 0xE000 4008 and TIMER1:
T1TC - 0xE000 8008)
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
15.5.5 Prescale Register (PR, TIMER0: T0PR - 0xE000 400C and TIMER1:
T1PR - 0xE000 800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
15.5.6 Prescale Counter Register (PC, TIMER0: T0PC - 0xE000 4010 and
TIMER1: T1PC - 0xE000 8010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the
resolution of the timer and the maximum time before the timer overflows. The Prescale
Counter is incremented on every PCLK. When it reaches the value stored in the Prescale
Register, the Timer Counter is incremented, and the Prescale Counter is reset on the next
PCLK. This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs
when PR = 1, etc.

15.5.7 Match Registers (MR0 - MR3)

The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.

User manual

TIMER1: T1TCR - address 0xE000 8070) bit description
Symbol Value Description
Count When bits 1:0 in this register are not 00, these bits select
Input which CAP pin is sampled for clocking:
Select
00 CAPn.0 (CAP0.0 for TIMER0 and CAP1.0 for TIMER1)
01 CAPn.1 (CAP0.1 for TIMER0 and CAP1.1 for TIMER1)
10 CAPn.2 (CAP0.2 for TIMER0 and CAP1.2 for TIMER1)
11 CAP1.3 for TIMER1
Note: If Counter mode is selected for a particular CAPn input
in the TnCTCR, the 3 bits for that input in the Capture Control
Register (TnCCR) must be programmed as 000. However,
capture and/or interrupt can be selected for the other 3 CAPn
inputs in the same timer.
Note: CAP0.3 not available on Timer 0.
- - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 15: Timer0 and Timer1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
00
NA
192