A/D Status Register (Adstat, Adc0: Ad0Cr - 0Xe003 4004); A/D Interrupt Enable Register (Adinten, Adc0: Ad0Inten - 0Xe003 400C); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

14.4.3 A/D Status Register (ADSTAT, ADC0: AD0CR - 0xE003 4004)

The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Table 161: A/D Status Register (ADSTAT, ADC0: AD0STAT - address 0xE003 4004 and ADC1: AD1STAT - address
0xE006 0004) bit description
Bit Symbol Description
0 DONE0 This bit mirrors the DONE status flag from the result register for A/D channel 0.
1 DONE1 This bit mirrors the DONE status flag from the result register for A/D channel 1.
2 DONE2 This bit mirrors the DONE status flag from the result register for A/D channel 2.
3 DONE3 This bit mirrors the DONE status flag from the result register for A/D channel 3.
4 DONE4 This bit mirrors the DONE status flag from the result register for A/D channel 4.
5 DONE5 This bit mirrors the DONE status flag from the result register for A/D channel 5.
6 DONE6 This bit mirrors the DONE status flag from the result register for A/D channel 6.
7 DONE7 This bit mirrors the DONE status flag from the result register for A/D channel 7.
8 OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.
9 OVERRUN1 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.
10 OVERRUN2 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.
11 OVERRUN3 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.
12 OVERRUN4 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.
13 OVERRUN5 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.
14 OVERRUN6 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.
15 OVERRUN7 This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.
16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done
flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
31:17 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
14.4.4 A/D Interrupt Enable Register (ADINTEN, ADC0: AD0INTEN -
0xE003 400C)
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent results
are read by the application program whenever they are needed. In this case, an interrupt
is not desirable at the end of each conversion for some A/D channels.
Table 162: A/D Status Register (ADSTAT, ADC0: AD0STAT - address 0xE003 4004 ) bit description
Bit Symbol Value
0 ADINTEN0 0
1
1 ADINTEN1 0
1

User manual

Description
Completion of a conversion on ADC channel 0 will not generate an interrupt.
Completion of a conversion on ADC channel 0 will generate an interrupt.
Completion of a conversion on ADC channel 1 will not generate an interrupt.
Completion of a conversion on ADC channel 1 will generate an interrupt.
Rev. 01 — 12 January 2006
UM10161
Chapter 14: A/D converter
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NA
Reset
value
0
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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