Vector Address Registers 0-15 (Vicvectaddr0-15 - 0Xffff F100-13C); Default Vector Address Register (Vicdefvectaddr - 0Xffff F034); Vector Address Register (Vicvectaddr - 0Xffff F030); Protection Enable Register (Vicprotection - 0Xffff F020) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

5.4.10 Vector Address registers 0-15 (VICVectAddr0-15 - 0xFFFF F100-13C)

These are a read/write accessible registers. These registers hold the addresses of the
Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.
Table 53: Vector Address registers (VICVectAddr0-15 - addresses 0xFFFF F100-13C) bit description
Bit Symbol
31:0 IRQ_vector

5.4.11 Default Vector Address register (VICDefVectAddr - 0xFFFF F034)

This is a read/write accessible register. This register holds the address of the Interrupt
Service routine (ISR) for non-vectored IRQs.
Table 54: Default Vector Address register (VICDefVectAddr - address 0xFFFF F034) bit description
Bit Symbol
31:0 IRQ_vector

5.4.12 Vector Address register (VICVectAddr - 0xFFFF F030)

This is a read/write accessible register. When an IRQ interrupt occurs, the IRQ service
routine can read this register and jump to the value read.
Table 55: Vector Address register (VICVectAddr - address 0xFFFF F030) bit description
Bit Symbol
31:0 IRQ_vector

5.4.13 Protection Enable register (VICProtection - 0xFFFF F020)

This is a read/write accessible register. It controls access to the VIC registers by software
running in User mode.
Table 56: Protection Enable register (VICProtection - address 0xFFFF F020) bit description
Bit Symbol
0 VIC_access
31:1 -
User manual
Description
When one or more interrupt request or software interrupt is (are) enabled,
classified as IRQ, asserted, and assigned to an enabled vectored IRQ slot,
the value from this register for the highest-priority such slot will be provided
when the IRQ service routine reads the Vector Address register -VICVectAddr
(Section 5.4.10).
Description
When an IRQ service routine reads the Vector Address register
(VICVectAddr), and no IRQ slot responds as described above, this address is
returned.
Description
If any of the interrupt requests or software interrupts that are assigned to a
vectored IRQ slot is (are) enabled, classified as IRQ, and asserted, reading
from this register returns the address in the Vector Address Register for the
highest-priority such slot (lowest-numbered) such slot. Otherwise it returns the
address in the Default Vector Address Register.
Writing to this register does not set the value for future reads from it. Rather,
this register should be written near the end of an ISR, to update the priority
hardware.
Value Description
0 VIC registers can be accessed in User or privileged mode.
1 The VIC registers can only be accessed in privileged mode.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 5: VIC
Reset value
0x0000 0000
Reset value
0x0000 0000
Reset value
0x0000 0000
Reset
value
0
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
52