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Philips Semiconductors
Volume 1
11.5.4 Slave Transmitter mode
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I
operate as a master and as a slave. In the slave mode, the I
slave address and the general call address. If one of these addresses is detected, an
interrupt is requested. When the microcontrollers wishes to become the bus master, the
hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, the I
interface switches to the slave mode immediately and can detect its own slave address in
the same serial transfer.
2
11.6 I
C implementation and operation
Figure 29
describes the individual blocks.
11.6.1 Input filters and output stages
Input signals are synchronized with the internal clock, and spikes shorter than three
clocks are filtered out.
User manual
S
SLAVE ADDRESS
From Master to Slave
From Slave to Master
Fig 27. Format of Slave Receiver mode
S
SLAVE ADDRESS
From Master to Slave
From Slave to Master
Fig 28. Format of Slave Transmitter mode
shows how the on-chip I2C-bus interface is implemented, and the following text
Rev. 01 — 12 January 2006
W
A
DATA
"0" - Write
"1" - Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START Condition
P = STOP Condition
RS = Repeated START condition
R
A
DATA
"0" - Write
"1" - Read
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START Condition
P = STOP Condition
UM10161
Chapter 11: I
A/A
A
DATA
Data Transferred
(n Bytes + Acknowledge)
2
C hardware looks for its own
A
DATA
Data Transferred
(n Bytes + Acknowledge)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C interfaces
P/RS
2
C may
2
C
A
P
123
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