C Control Set Register (I2Conset: I2C0, I2C0Conset - 0Xe001 C000 And I2C1, I2C1Conset - 0Xe005 C000); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
2
Table 120: I C register map
Name Description
I2SCLH SCH Duty Cycle Register High Half Word. Determines
the high time of the I
I2SCLL SCL Duty Cycle Register Low Half Word. Determines
the low time of the I
together determine the clock frequency generated by an
2
I C master and certain times used in slave mode.
2
I2CONCLR I C Control Clear Register. When a one is written to a
bit of this register, the corresponding bit in the I
register is cleared. Writing a zero has no effect on the
corresponding bit in the I
[1]
2
11.7.1 I
and I2C1, I2C1CONSET - 0xE005 C000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 121: I
Bit Symbol
1:0 -
2
3
4
5
6
7
I2EN I
cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I
interface is disabled.
When I2EN is "0", the SDA and SCL input signals are ignored, the I
addressed" slave state, and the STO bit is forced to "0".
I2EN should not be used to temporarily release the I
2
I
STA is the START flag. Setting this bit causes the I
transmit a START condition or transmit a repeated START condition if it is already in
master mode.

User manual

2
C clock.
2
C clock. I2nSCLL and I2nSCLH
2
C control register.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
C Control Set register (I2CONSET: I2C0, I2C0CONSET - 0xE001 C000
2
C interface. Writing a one to a bit of this register causes the
2
2
C Control Set register (I2CONSET: I2C0, I2C0CONSET - address 0xE001 C000
and I2C1, I2C1CONSET - address 0xE005 C000) bit description
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
AA Assert acknowledge flag. See the text below.
2
SI I C interrupt flag.
STO STOP flag. See the text below.
STA START flag. See the text below.
2
I2EN I C interface enable. See the text below.
- Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
C Interface Enable. When I2EN is 1, the I
C-bus status is lost. The AA flag should be used instead.
Rev. 01 — 12 January 2006
Access Reset
R/W
R/W
WO
2
C control
C control register to be set. Writing a zero has no effect.
2
UM10161
Chapter 11: I
2
I C0 Address
[1]
value and Name
0x04 0xE001 C010
I2C0SCLH
0x04 0xE001 C014
I2C0SCLL
NA 0xE001 C018
I2C0CONCLR
C interface is enabled. I2EN can be
2
C block is in the "not
2
C-bus since, when I2EN is reset, the
2
C interface to enter master mode and
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C interfaces
2
I C1 Address
and Name
0xE005 C010
I2C1SCLH
0xE005 C014
I2C1SCLL
0xE005 C018
I2C1CONCLR
Reset
value
NA
0
0
0
0
NA
2
C
128