Spi Format With Cpol=0,Cpha=1; User Manual - Philips LPC2101 User Manual

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In the case of a single word transmission, after all bits of the data word have been
transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last
bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSEL signal must be
pulsed HIGH between each data word transfer. This is because the slave select pin
freezes the data in its serial peripheral register and does not allow it to be altered if the
CPHA bit is logic zero. Therefore the master device must raise the SSEL pin of the slave
device between each data transfer to enable the serial peripheral data write. On
completion of the continuous transfer, the SSEL pin is returned to its idle state one SCK
period after the last bit has been captured.

13.3.5 SPI format with CPOL=0,CPHA=1

The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in
Figure
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SSEL master signal being driven LOW. Master's MOSI pin
is enabled. After a further one half SCK period, both master and slave valid data is
enabled onto their respective transmission lines. At the same time, the SCK is enabled
with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSEL line is
returned to its idle HIGH state one SCK period after the last bit has been captured.
For continuous back-to-back transfers, the SSEL pin is held LOW between successive
data words and termination is the same as that of the single word transfer.

User manual

43, which covers both single and continuous transfers.
SCK
SSEL
MOSI
MISO
Fig 43. Motorola SPI frame format (single transfer) with CPOL=0 and CPHA=1
•
The CLK signal is forced LOW
•
SSEL is forced HIGH
•
The transmit MOSI/MISO pad is in high impedance
Rev. 01 — 12 January 2006
MSB
Q MSB
4 to 16 bits
UM10161
Chapter 13: SSP
LSB
LSB Q
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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