Sony BVW-55 Maintenance Manual page 559

AK5352-VF-E2 (ASAHI)
C-MOS 20-BIT A/D CONVERTER
—TOP VIEW—
AINR+ 1 VB 24
IN
AINR_ 2 23 SMODE1
IN IN
VREF 3 22 CMODE
OUT IN
4 VA 21 SDATA
OUT
5 A GND 20 FSYNC
I/O
R
AINL+ 6 19 L/
IN I/O
AINL_ 7 18 SCLK
IN I/O
TST1 8 17 MCLK
IN
PD
HPFE 9 16
IN IN
TST2 10 15 SMODE2
IN
TST3 11 14 TST4
D GND
12 VD 13
INPUT
AINL+ : CHANNEL L ANALOG POSITIVE INPUT
AINL_ : CHANNEL L ANALOG NEGATIVE INPUT
AINR+ : CHANNEL R ANALOG POSITIVE INPUT
AINR_ : CHANNEL R ANALOG NEGATIVE INPUT
CMODE : MASTER CLOCK SELECT
( L : MCLK = 256 fs )
( H : MCLK = 384 fs )
HPFE : HIGH PASS FILTER ENABLE
(L : OFF)
(H : ON)
MCLK : MASTER CLOCK
( CMODE = H : 384 fs )
( CMODE = L : 256 fs )
PD
: POWER DOWN
(L : POWER DOWN MODE)
SMODE1, SMODE2 : INTERFACE CLOCK SELECT
SMODE1 SMODE2
MODE
L L SUB MODE
H L
MASTER MODE
L H SUB MODE
H H
MASTER MODE
OUTPUT
SDATA : SERIAL DATA
VREF : REFERENCE VOLTAGE
INPUT/OUTPUT
FSYNC : FRAME SYNC CLOCK
R
L/ : INPUT CHANNEL SELECT
( SUB MODE : fs CLK INPUT )
( MASTER MODE : fs CLK OUTPUT )
SCLK : SERIAL DATA CLOCK
( SUB MODE : 64 fs CLK INPUT )
( MASTER MODE : 64 fs CLK OUTPUT )
15
SMODE2
23
SMODE1
6
AINL+
∑
T
7 MODULATOR
AINL_
DIGITAL
DECIMATION
FILTER
1
AINR+
∑
T
2 MODULATOR
AINR_
VOLTAGE
3
VREF
REFERENCE
22
CMODE
CLOCK
17
DIVIDER
MCLK
16
PD POWER DOWN
9
HPFE HIGH PASS FILTER ENABLE
BVW-55
6
AINL+
7
AINL_
1
AINR+
2
AINR_
21
SDATA
22
CMODE
17 18
MCLK SCLK
23 19
SMODE1 L/R
15 20
SMODE2 FSYNC
3
VREF
9
HPFE
16
PD
8
TST1
10
TST2
11
TST3
14
TST4
LRCK
H/L
H/L
L/H
L/H
21
SDATA
18
SERIAL
SCLK
OUTPUT
19
R
L/
INTERFACE
20
FSYNC
AK6420AF-E2 (ASAHI)
C-MOS 2,048 ( 128 x 16 ) -BIT EEPROM
—TOP VIEW—
BUSY
RDY/ 1 8 RESET
2 V GND 7
DD
CS
3 6 DO
SK
4 5 DI
5 INSTRUCTION
DI
REGISTER
8
INSTRUCTION
DECODER
CONTROL
3
CS
AND
CLOCK
GENERATION
4
SK
8
RESET
AM26LS32ACNS (TI)
AM26LS32ACNS-E05
HIGH SPEED DIFFERENTIAL LINE RECEIVER
—TOP VIEW—
EN2
16 15 14 13 12 11 10 9
V
CC
_ + + _
GND
1 2 3 4 5 6 7 8
C32/LS32
LS33
INPUT
CS
: CHIP SELECT
DI : DATA INPUT
RESET : RESET
SK
: SERIAL CLOCK
OUTPUT
DO : DATA OUTPUT
BUSY
RDY/ : READY/BUSY
DATA
REGISTER
R/W
16 16
AMPS
AND
AUTO
ERASE
ADD
7 14 DECODER 14
BUFFERS
VPP SW
V REF
FUNCTION TABLE
EN2 EN1 OUTPUT
0 0 ENABLE
0 1 ENABLE
1 0 HI-Z
1 1 ENABLE
0 : LOW LEVEL
1 : HIGH LEVEL
HI-Z : HIGH IMPEDANCE
SENSE INPUT VOLT
±200mV ±7 V
±500mV ±15 V
IC
6
DO
EE
PROM
2048-BIT
( 128 x 16 )
VPP
GENERATOR
1
BUSY
RDY/
2-9