Sony BVW-55 Maintenance Manual page 605

Hide thumbs Also See for BVW-55:
Table of Contents

Advertisement

PERIPHERAL INTERFACE
BLOCK
SIO (µPD72001) INTERFACE
S-RAM INTERFACE
21, 24 - 28
A23 - 28
19, 20
A0, A1
150
DATAENN
151
FIFO (µPD42280) INTERFACE
BURSTN
152
LASTN
153
RDN
154
WRN
131
VARWAITN
CPU PERIPHERAL
15 - 18
INTERFACE
BEN0 - 3
47
RESETN
149
SYSCLKN
ADDRESS DECODER
29 - 36
D0 - 7
PERIPHERAL BLOCK
INTERRUPT
135 - 142
INTP0 - 7
CONTROLLER
PIO 1
PIO 2
4, 7, 10
CTC1CLK0 - 2
5, 8, 11
CTC 1
CTC1G0 - 2
120, 123, 126
CTC2CLK0 - 2
CTC 2
121, 124, 127
CTC2G0 - 2
48
SIO BLOCK
SIOCLK
( BAUD RATE GEN )
52
SIO2CTS
SIO 1
53
SIO2DSR
SIO 2
145
EXTFRAME
FRAME GEN
HALF CLK GEN
BVW-55
59
SIOCDN
60
SIOBAN
57
SIORDN
58
SIOWRN
38
SRAM1CS
39
SRAM2CS
40 - 43
WRENNA - D
165 - 168
FIFOREN1 - 4
169 - 172
FIFOWEN1 - 4
173
FIFORCKN
155
ACKN
156
RDCENN
14, 174
IOENN, 2
2
RDENN
3
WRENN
13
EXTDENN
158 - 163
S8W3CSN1 - 6
164
V8W3CSN
148
S8W4CSN
130
V8W6CSN
118
S16W2CSN
119
S16W3CSN
37
FLASHCSN
143
INT
61 - 68
PIO1P00 - 07
70 - 77
PIO1P10 - 17
79 - 86
PIO1P20 - 27
90 - 97
PIO2P00 - 07
99 - 106
PIO2P10 - 17
108, 109, 112 - 117
PIO2P20 - 27
6, 9, 12
CTC1OUT0 - 2
122, 125, 128
CTC2OUT0 - 2
49
SIO1TXD
50
SIO1RXD
51
SIO1INT
54
SIO2TXD
55
SIO2RXD
56
SIO2INT
144
SIO2BRK
147
VINT
146
FRAME
129
HALFCLK
CXK1203AR (SONY)
CXK1203AR-T4
C-MOS DIGITAL LINE MEMORY
—TOP VIEW—
37
NC
24
38
23
NC
39
22
40
21
41
20
V
42
DD
19
43
18
V
DD
44
NC
17
45
16
NC
46
NC
15
47
NC
14
48
13
NC
PIN
PIN
PIN
I/O
SIGNAL
I/O
SIGNAL
NO.
NO.
NO.
1
I
D0
13
I
PSW7
25
2
I
D1
14
I
PSW6
26
3
I
D2
15
I
PSW5
27
4
I
D3
16
I
PSW4
28
5
I
D4
17
I
PSW3
29
6
GND
18
I
PSW2
30
7
I
D5
19
V
31
DD
8
I
D6
20
I
PSW1
32
9
I
D7
21
I
PSW0
33
10
I
D8
22
I
PSB2
34
11
I
D9
23
I
PSB1
35
12
I
TINT
24
I
PSB0
36
AEN
: LINE MEMORY SELECT
CLK
: CLOCK
DIN0 - DIN9
: VIDEO DATA INPUT
DOT0 - DOT9
: VIDEO DATA OUTPUT
N/P
: NTSC/PAL/SECAM SELECT
OEN
: OUTPUT ENABLE
PSB0 - PSB2
: DELAY STEP SELECT (1-BITxN)
PSW0 - PSW7
: DELAY STEP SELECT (8-BITxN)
SCLK
: CLOCK EDGE SELECT
TINT
: TEST
1 - 5
7 - 11
DIN0
1 LINE MEMORY
BUFF
(1138 x 10-BIT)
DIN9
ADDRESS
COUNTER
13 - 18
20, 21
PSW0
ADDRESS
MULTIPLEXER
PSW7
40
N/P
39
AEN
PIN
I/O
SIGNAL
I/O
SIGNAL
NO.
OEN
I
37
NC
O
DOT9
38
NC
O
DOT8
39
I
AEN
I
O
DOT7
40
N/P
O
DOT6
41
I
SCLK
I
GND
42
CLK
O
DOT5
43
V
DD
O
DOT4
44
NC
O
DOT3
45
NC
O
DOT2
46
NC
O
DOT1
47
NC
O
DOT0
48
NC
26 - 29
31 - 36
SMALL DELAY
BUFF
CONTROLLER
DOT0
DOT9
25
OEN
PSB0
22-24
PSB2
42
TIMING
CLK
41
CONTROLLER
SCLK
12
TINT
2-55
IC

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents