Sony BVW-55 Maintenance Manual page 639

UPD72001GC-11-3B6 (NEC)
C-MOS ADVANCED MULTI-PROTOCOL SERIAL CONTROLLER
—TOP VIEW—
40 NC NC
41 NC NC
42
43
44
45 V
DD
46 V GND
DD
47 CK GND
48
49
50 NC
51 NC
52 NC NC
PIN PIN
I/O SIGNAL I/O
NO. NO.
1 O TxDA 19 —
TRxCA
2 I/O 20 —
SYNCA
3 I/O XI2A/ 21 I
STRxCA
4 I XI1A/ 22 I
5 I RxDA 23 I
CTSA
6 I 24 I
7 — NC(OPEN) 25 —
DCDA
8 I 26 —
9 I/O D7 27 O
10 I/O D6 28 I
11 I/O D5 29 I
12 I/O D4 30 O
13 I/O D3 31 I
14 — NC 32 I
15 I/O D2 33 — NC(OPEN)
16 — NC 34 I/O
17 I/O D1 35 I
18 I/O D0 36 I XI1B/
CLOCK/
47
CK STANDBY
CONTROL
DATA BUS
D7 - D0
BUFFER
22
RD
11
WR
READ/
23
WRITE
C/D
24
CONTROL
B/A
48
RESET
49
DRQRxA
44
DMA
DRQTxA
42
CONTROL
DTRB/DRQRxB
43
DTRA/DRQTxB
30
INT
29
INTAK
INTERRUPT
28
CONTROL
PRI
27
PRO
INPUTS
FUNCTION
WR RD B/A C/D
0 CHANNEL A
0 1 0 WRITE (TxD)
1 CHANNEL B
0 CHANNEL A
1 0 0 READ (RxD)
1 CHANNEL B
0 CHANNEL A
0 1 1 WRITE (CONTROL REGISTER)
1 CHANNEL B
0 CHANNEL A
1 0 1 READ (STATUS REGISTER)
1 CHANNEL B
1 1 x x
HIGH-IMPEDANCE
0 0 x
x INHIBIT
0 : LOW LEVEL
1 : HIGH LEVEL
x : DON'T CARE.
BVW-55
26
25
24
23
22
21
20
19
18
17
16
15
14
PIN
SIGNAL I/O SIGNAL
NO.
SYNCB
GND 37 I/O X12B/
GND 38 O TxDB
WR
RTSB
39 O
RD
40 — NC
D
C/ 41 — NC
A
DTRB
B/ 42 O /DRQRxB
DTRA
NC 43 O /DRQTxB
NC 44 O DRQTxA
PRO
45 — V
DD
PRI
46 — V
DD
INTAK
47 I CK
INT
RESET
48 I
CTSB
49 O DRQRxA
DCDB
RTSA
50 O
51 — NC
TRxCB
52 — NC
RxDB
STRxCB
XI1B/
RTSB TRxCB STRxCB
39 34 36
CHANNEL B
INTERNAL BUS
CHANNEL A
CR0-CR5 CONTROL
BRG-H, L SR12-SR15
SIGNAL
CR10-CR15
TxRx CLOCK
BRG DPLL
RxCLK
TxRx CLOCK
CONTROL
TxCLK
OSC
50 2 4
RTSA TRxCA XI1A/
STRxCA
CK : SYSTEM CLOCK INPUT
WR : WRITE ENABLE INPUT
RD : READ ENABLE INPUT
A
B/ : CHANNEL B/
d
C/ : CONTROL/
D0 - D7 : DATA BUS INPUTS/OUTPUTS
INT : INTERRUPT OUTPUT
INTAK : INTERRUPT ACKNOWLEDGE INPUT
PRI : PRIORITY INPUT
DRQTxA : DMA REQUEST TxA OUTPUT
DRQRxA : DMA REQUEST RxA OUTPUT
PRO : PRIORITY OUTPUT
XI2B/
SYNCB DCDB CTSB RxDB
37 32 31 35 38
CR8, CR9 CR6,
SR8, SR9 CR7
SR0 Rx
0 - 3 4 - 7 BUFF
SR1 - SR4
SR10, SR11
TxRx CONTROL TRANSMITTER
RECEIVER
3 8 6 5 1
XI2A/ DCDA CTSA RxDA TxDA
SYNCA
DTRA
/DRQTxB
DTRB
/DRQRxB
CTSA, CTSB
A
SELECT INPUT DCDA, DCDB
DATA
SELECT INPUT RTSA, RTSB
RESET
TxDB
5
RxDA
6
CTSA XI2A/SYNCA
8
DCDA
4
XI1A/STRxCA
35
RxDB
31
CTSB XI2B/SYNCB
32
DCDB
36
XI1B/STRxCB
47
ø
Tx
22
BUFFER
RD
21
WR
23
C/D
24
B/A
48
RESET
DTRB/DRQRxB
DTRA/DRQTxB
29
INTAK
28
PRI
: DATA TERMINAL READY A/DMA REQUEST TxB OUTPUT
: DATA TERMINAL READY B/DMA REQUEST RxB OUTPUT
: CLEAR TO SEND A/B INPUT
: DATA CARRIER DETECT A/B INPUT
: REQUEST TO SEND A/B OUTPUT
: RESET INPUT
IC
1
TxDA
3
2
TRxCA
50
RTSA
38
TxDB
37
34
TRxCB
39
RTSB
18
D0
17
D1
15
D2
13
D3
12
D4
11
D5
10
D6
9
D7
49
DRQRxA
44
DRQTxA
42
43
30
INT
27
PRO
2-89