Sony BVW-55 Maintenance Manual page 565

CXB1341R (SONY)
SERIAL DIGITAL INTERFACE TRANSMISSION ENCODER
—TOP VIEW—
49 V
CCT
50
51
52
53
54
55
56
57
58
59
60
61
GND
62
63
V
CCL
64
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 — V 17 — NC
CCL
2 I D1X 18 — NC
3 I D1Y 19 — V
CCL
4 I D0X 20 I MDS
5 I D0Y 21 — NC
6 I PCX 22 I BCAP
7 I PCY 23 — V
CCL
8 I SCKX 24 I ICP
9 I SCKY 25 — GND
10 I TEST 26 O CPX
11 I RESET 27 O CPY
12 — V 28 — V
CCT CCL
13 — V 29 I FSR0
CCL
14 — GND 30 I FSR1
15 — GND 31 I FSR2
16 — NC 32 I FSR3
INPUT
BCAP : EXTERNAL CAPACITOR FOR VCO
D9X - D0X : POSITIVE PARALLEL DATA
D9Y - D0Y : NEGATIVE PARALLEL DATA
ETS : 8-BIT/10-BIT SELECT (L = 8-BIT, H OR OPEN = 10-BIT)
FSR0 - FSR3 : EXTERNAL RESISTOR FOR SETTING THE FREE-RUN FREQUENCY OF VCO
ICP : EXTERNAL RESISTOR FOR CHARGE PUMP
MDS : TEST
MOD0, MOD1 : VCO RATE SELECT
PCX : POSITIVE PARALLEL CLOCK
PCY : NEGATIVE PARALLEL CLOCK
RESET : PLL RESET
SCKX, SCKY : TEST
TEST : TEST
THRU : TEST
OUTPUT
LST : PLL LOCK STATUS
PCK : PARALLEL CLOCK
CPX, CPY : CHARGE PUMP
SX, SY : EXTERNAL RESISTOR FOR SERIAL DIFFERENTIAL
PARALLEL CLK
47
D9X
48
D9Y
50
D8X
51
D8Y
52
D7X
53
D7Y
54
D6X
55
D6Y
56
D5X
57
D5Y
58
D4X
59
D4Y
60
D3X
61
D3Y
62
D2X
63
D2Y
2
D1X
LOAD PULSE
3
D1Y
4
1/10 COUNTER
D0X
5
D0Y
90d SIFT PSK
6
PCX
7
PCY
8
SCKX
9
SCKY
LOCK PHASE
DET. COMP.
CHARGE
RESET
PUMP
BVW-55
32
31
30
29
V 28
CCL
27
26
GND 25
24
V 23
CCL
22
NC 21
20
V 19
CCL
NC 18
NC 17
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
33 — GND 49 — V
CCT
34 I MOD0 50 I D8X
35 I MOD1 51 I D8Y
36 — V 52 I D7X
CC2
37 O LST 53 I D7Y
38 I THRU 54 I D6X
39 — GND 55 I D6Y
40 — GND 56 I D5X
41 O SX 57 I D5Y
42 — V 58 I D4X
CCS
43 O SY 59 I D4Y
44 — V 60 I D3X
CCL
45 I ETS 61 I D3Y
46 O PCK 62 I D2X
47 I D9X 63 I D2Y
48 I D9Y 64 — GND
SERIAL CLK
_
_
1/2
FREE RUN SET
VCO
CXD101-106Q (SONY)
C-MOS DIGITAL DELAY LINE
—TOP VIEW—
37
38
39
40
41 NC
42
43 V
DD
44 NC
45 NC
46
47
48
INPUT
CLK ; CLOCK
DIN0 - DIN10 ; DATA
DOP ; DO PULSE
MODE ; H : 14CK DELAY
L : 5CK DELAY
OEN ; OUTPUT ENABLE
L : DOT0-10 OUTPUT STATUS
(
H : HIGH IMPEDANCE STATUS
TINT ; H : MPU COMMUNICATION MODE
SCK ; MPU SERIAL I/F CLOCK
SIN ; MPU SERIAL DATA IN
STB ; MPU SERIAL I/F STROBE
YC ; L : CHROMA, H : Y
DG1-DG3 ; FOR DIAG
LTP ; FOR DIAG
CP2 ; TEST TERMINAL GENERALLY USE : L
INV ; TEST TERMINAL GENERALLY USE : L
OUTPUT
DOT0 - DOT10 ; DATA
SDO ; STRETCHED DO
SOUT ; DATA OUT TO MPU
TOT ; TEST
PIN PIN
I/O SIGNAL I/O
NO. NO.
1 I DIN0 13 O
2 I DIN1 14 I
3 I DIN2 15 I
4 I DIN3 16 I
5 I DIN4 17 I
6 — GND 18 —
7 I DIN5 19 —
8 I DIN6 20 I
9 I DIN7 21 I
10 I DIN8 22 I
11 I DOP 23 I
12 I TINT 24 I
1 - 5, 7 - 10,
11
47, 48
4 CLOCK
DIN0 - 10
DELAY
42
CLK
46
PCK
24
MODE
43
SY
11
41
14 CLOCK
SX DOP
DELAY
25
OEN
14
38
SCK
THRU
15
SIN
16
MPU
STB
17
INTERFACE
YC
45
ETS
DG1 - 3
20 - 23
LTP
4
10
TEST
12
TINT
37
LST
20
MDS
35
MOD1
34
MOD0
36
1
DIN0 DOT0
2 35
DIN1 DOT1
3 34
DIN2 DOT2
24
4 33
DIN3 DOT3
23
5 32
DIN4 DOT4
22
7 31
DIN5 DOT5
21
8 29
DIN6 DOT6
20
9 28
DIN7 DOT7
V 19
DD
10 27
DIN8 DOT8
NC 18
38
47
DIN9 DOT9
17
48 37
DIN10 DOT10
16
15
11 26
DOP SDO
14
24
MODE
13
25
OEN
14
SCK
15
SIN
16
STB
17 13
YC SOUT
20
LTP
21
DG1
22
DG2
23
DG3
)
12
TINT
39 46
INV TOT
40
CP2
42
PIN PIN
SIGNAL I/O SIGNAL I/O
NO. NO.
SOUT 25 I OEN 37 O
SCK 26 O SDO 38 O
SIN 27 O DOT8 39
STB 28 O DOT7 40
YC 29 O DOT6 41 —
NC 30 — GND 42
V 31 O DOT5 43 —
DD
LTP 32 O DOT4 44 —
DG1 33 O DOT3 45 —
DG2 34 O DOT2 46 O
DG3 35 O DOT1 47
MODE 36 O DOT0 48
9
9 CLOCK
DELAY D Q
11
11
IC
SIGNAL
DOT10
DOT9
I INV
I CP2
NC
I CLK
V
DD
NC
NC
TOT
I DIN9
I DIN10
27 - 29,
31 - 38
DOT0
26
SDO
13
SOUT
2-15