Sony BVW-55 Maintenance Manual page 578

IC
CXD2221Q (SONY)
C-MOS WRITE CLOCK GENERATORE FOR TBC
—TOP VIEW—
81
D GND
85
90
95
A V
DD
100
PIN PIN
I/O SIGNAL I/O SIGNAL
No. No.
1 O PB SYNC 21 — A V
2 I H BLKG 22 I COP I
3 I VIN 4 23 I COP X
4 I REF 3 24 O COP O
5 I VIN 3 25 I SWP
6 O VOT 3 26 I TST
7 I AI 3 27 I WRITE V
8 I ACPI 28 I TEST0
9 — A GND 29 I TEST1
10 I ACP X 30 I EOP X
11 O ACP O 31 O EOP O
12 I MD1 32 — A GND
13 I COUNT H 33 I AI 2
14 I BOP X 34 I DOP I
15 O BOP O 35 I DOP X
16 O ER 1 36 O DOP O
17 O ER 2 37 I VCO I
18 I MD2 38 I VCO EN
19 I CLR 39 O DIAG
20 I Y/C 40 I DSEL
2-28
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
No. No. No.
41 O ADSW 61 O WCP 81
DD
42 O GB OUT 62 O ACP 82
43 O TEST OUT0 63 O TOUT 83
44 O TEST OUT1 64 O PBV/CCP 84
45 I TEST IN2 65 O AZ1 85
46 I TEST IN3 66 O WZ 86
47 I PLL RESET 67 I WCK 87
48 — D V 68 O GCK 88
DD
49 I DDF 69 O AD WCK 89
50 O SH OUT 70 O AD WCK 90
51 I PB/EE 71 — D V 91
DD
52 I NOSIG 72 O CH 92
53 I FR30 73 O SH2 93
54 I R20 74 O CP 94
55 I FBID 75 I ERR IN 95
56 I DO 76 I SVLK 96
57 I GBI 77 I SVD 97
58 I SHW 78 I IEC OFF 98
59 — D GND 79 O IOCK 99
60 I GH 80 O CS 100
INPUT
; COMPARATOR ( + )
ACP I
; COMPARATOR ( _ )
ACP X
; CURRENT SOURCE
50 AI 2, 3
; OP AMP A ( + ) ( REFERENCE VOLTAGE 0.7 V )
AOP I
; OP AMP A ( _ )
D V
DD AOP X
FOR SAWTOOTH WAVE GENERATION OF PB SYNC NOISE REJECTOR
; OP AMP B ( _ )
45 BOP X
FOR SAWTOOTH WAVE GENERATION OF PLL PHASE COMPARATOR
; REFERENCE VOLTAGE ( 3.8 V )
CCPI
; CHROMA WRITE CLAMP PULSE TIMING SHIFT
CLP TIM
; CLEAR
CLR
; OP AMP C (+)
40 COP I
; OP AMP C ( _ )
COP X
; COUNT H
COUNT H
; DOUBLE-DIFFERENTIAL PULSE
DDF
; DROP-OUT PULSE
DO
; REFERENCE VOLTAGE INPUT FOR PLL ERROR AMP
35 DOP I
; PLL ERROR AMP INPUT 2
DOP X
; A/D SELECT ( CONNECT TO PIN 41 )
DSEL
; PLL ERROR AMP INPUT 1
EOP X
A GND
; ERROR IN ( 8 BITS, SERIAL ) FROM IMPACT ERROR COMPENSATION
31 ERR IN
; FAST BIDIREX MODE
FBID
; FORWARD/REVERSE 30 OR OVER TIMES MODE
FR30
; GUARD BAND ( H ; PLL PHASE COMPARATE ENABLE )
GBI
; GATED H
GH
; H BLANKING PULSE
H BLKG
I/O SIGNAL ; IMPACT ERROR COMPENSATION DISABLE
IEC OFF
; MODE SELECT ( H ; 525, L ; 625 )
MD1
O DO 0
; MODE SELECT ( H ; 13.5 MHz, L ; 14.3 MHz )
MD2
— D GND
; NO SIGNAL STATUS
NOSIG
O DO 1
; PB SYNC
PB SY
O DO 2
; MODE SELECT ( H ; E-E MODE, L ; PB MODE )
PB/EE
O DO 3
; PLL COUNTER RESET
PLL RESET
O DO 4
; FREQUENCY CONTROL OF AD WCK ( L ; HALF, H ; NORMAL )
R20
O DO 5
; CLAMP LEVEL IN FOR SYNC SEPARATOR
REF 1
O DO 6
; SLICE LEVEL IN FOR SYNC SEPARATOR
REF 2
O DO 7
; CLAMP LEVEL IN FOR H BLANKING GENERATOR
REF 3
I CLP TIM
; SWITCHING WINDOW PULSE
SHW
I VIN 2
; SERVO LOCK VD
SVD
I REF 1
; SERVO LOCK SIGNAL
SVLK
I REF 2
; SWITCHING PULSE
SWP
I VIN 1
; FOR TEST
TEST IN 2, 3
I AOP I
; FOR TEST
TEST0, 1
I AOP X
; FOR TEST
TST
O AOP O
; INTERNAL VCO ENABLE
VCO EN
— A V
DD
; INTERNAL VCO ERROR VOLTAGE
VCO I
I PB SY
; VIDEO IN FOR FINE SYNC SEPARATOR
VIN 1
I CCP I
; VIDEO IN FOR ROUGH SYNC SEPARATOR
VIN 2
; VIDEO IN FOR H BLANKING GENERATOR
VIN 3
; VIDEO IN FOR MIX SYNC SEPARATOR
VIN 4
; WRITE CLOCK
WCK
; WRITE V
WRITE V
; MODE SELECT ( H ; Y MODE, L ; C MODE )
Y/C
OUTPUT
; ADVACE WRITE CLAMP PULSE
ACP
; COMPARATOR
ACP O
; WRITE CLOCK FOR A/D CONVERTER
AD WCK
; A/D SWITCH (CONNECT TO PIN 40)
ADSW
; A SAWTOOTH WAVE FOR PB SYNC NOISE REJECT
AOP O
; ADVANCE WRITE ZERO
AZ1
; A SAWTOOTH WAVE FOR PLL PHASE COMPARATE
BOP O
; COUNT H
CH
; CLAMP PULSE FOR IMPACT ERROR COMPENSATION
CP
; CHIP SELECT FOR IMPACT ERROR A/D CONVERTR
CS
; DIAGNOSTIC
DIAG
; IMPACT ERROR COMPENSATION DATA ( 8 BITS )
DO 0 - 7
; PLL ERROR AMP OUTPUT 2
DOP O
; PLL ERROR
ER 1
; AFC ERROR
ER 2
; PLL ERROR AMP OUTPUT 1
EOP O
; GUARD BAND
GB OUT
; GATED WRITE CLOCK
GCK
; CLOCK FOR IMPACT ERROR A/D CONVERTER
IOCK
; PB SYNC
PB SYNC
; Y MODE; PB V
PBV/CCP
C MODE; CENTER WRITE CLAMP PULSE FOR CTDM SIGNAL
; SAMPLING & HOLD PULSE
SH OUT
; SAMPLING PULSE FOR AFC
SH2
; FOR TEST
TEST OUT0, 1
; FOR TEST
TOUT
; H BLANKING
VOT 3
; WRITE CLAMP PULSE
WCP
; WRITE ZERO
WZ
BVW-55