Sony BVW-55 Maintenance Manual page 567

CXD104-114Q (SONY)
C-MOS MEMORY SEQUENCER (WRITE V CONTROL, VISC CONTROL)
—TOP VIEW—
52
53
54
55
56
57 GND
58 V
DD
59
60
61
62
63
64
PIN PIN PIN
I/O I/O
SIGNAL SIGNAL
No. No. No.
1 I WCK 17 O BIDDIR 33
2 I TIN0 18 O CNTV 34
I/O
3 I DIAG1 19 YBID 35
4 I DIAG2 20 O YGINC 36
5 I DIAG3 21 I YINC 37
6 I TMOD 22 I RZ 38
7 I RVD 23 I HCK 39
8 I REF O/E 24 I READ CONT 40
9 I SWP 25 — GND 41
10 — GND 26 — V 42
DD
11 O PB2H 27 O NORPB 43
I/O
12 CBID 28 I VISC EX 44
13 O SYMX 29 O SOUT 45
14 O PSW 30 I SCK 46
15 O TOT0 31 I SIN 47
16 I PB V 32 I STB 48
INPUT
21 20
YINC YGING
CINC ; C INC0
40 41
CLR ; CLEAR
CINC CGING
CWZ ; WRITE ZERO OF CHROMA SYSTEM
16 11 DIAG1 - 3 ; INPUT FOR DlAGNOSlS
PB V
PB2H
DT ; DT PLAYBACK DESIGNATE
1
WCK
DTV ; DT V
44
W O/E
FRB ; FAST REVERSE BIDIREX
56 60
SVV WV 1 HCK ; REFERENCE CLOCK (13.5MHz)
61
H SHIFT ; H SHIFT ENABLE
WV 2
MODE ; L ; 625 / H ; 525 MODE
NOS ; NO SIGNAL
9 13
SWP
SYMX
PB O/E ; PLAYBACK ODD/EVEN
48 14
FRB
PSW
PB V ; PLAYBACK V
49 34
RSH
FCP
READ CONT ; READ CONTROL (FROM CXD206-104Q)
47
XINS REF O/E ; REFERENCE ODD/EVEN
24
RSH ; RETURN SH
READ CONT
38
RVD ; RETURN VD
VISC CONT
RZ ; READ ZERO
55 50
DTV
SQV
SCK ; MPU SERlAL INTERFACE CLOCK
52
DT
SHW ; SH WlNDOW
36 27
V SHIFT
NORPB
SIN ; MPU SERIAL DATA IN
37
33
H SHIFT
VISC RST STB ; MPU SERIAL INTERFACE STROBE
28 35
SVV ; SERVO V
VISC EX
VISC DET
8 SWP ; SWITCHlNG PULSE
REF O/E
TIN0 ; TEST IN
39
PB O/E
TMOD ; TEST MODE
WCK ; WRITE CLOCK
23
HCK VISC CONT ; VISC CONTROL (FROM CXD206-104Q)
VISC EX ; PLAYBACK VISC EXIST
22
19
V SHIFT ; V SHIFT ENABLE
RZ YBID
63 YINC ; Y INC0
12
YWZ CBID
YGH ; Y GATED H
54
17
CWZ
BIDDIR
YWZ ; WRlTE ZERO OF Y SYSTEM
7
18
RVD
CNTV OUTPUT
62
64
BIDDIR ; DIRECTION CONTROL (H ; FORWARD/L ; REVERSE)
SHW GSHW
CGINC ; C GATED lNC0
43 CNTV ; COUNTER V
MODE
FCP ; FIELD CLAMP PULSE
3
DIAG 1
GSHW ; GATED SH WINDOW
4
DIAG 2
NORPB ; DETECTION OUT OF DT/NORMAL PLAYBACK
5
DIAG 3 PB2H ; PLAYBACK 2H
59
PSW ; QUASI-SWITCHING PULSE
CLR
53
SOUT ; MPU SERIAL DATA OUT
NOS
SQV ; V FOR MEMORY CONTROL
51
YGH
SYMX ; SYNC MlX CONTROL PULSE
32
STB
TOT0 - 2 ; TEST OUT
31 29
SIN SOUT
VISC DET ; VISC PHASE COMPARATOR ENABLE
30
SCK VISC RET ; VISC CONTROL RESET PULSE
15
W O/E ; WRITE ODD/EVEN
TOT 0
2
45 WV 1, 2 ; WRlTE V1, V2
TIN 0 TOT 1
6 XINS ; CRYSTAL INSERT PULSE
46
TMOD TOT 2
YGINC ; Y GATED INC0
INPUT/OUTPUT
CBID ; CHROMA SYSTEM BIDIREX
YBID ; Y SYSTEM BIDIREX
BVW-55
32
31
30
29
28
27
V 26
DD
GND 25
24
23
22
21
20
PIN
I/O I/O
SIGNAL SIGNAL
No.
O VISC RST 49 I RSH
O FCP 50 O SQV
O VISC DET 51 I YGH
I V SHIFT 52 I DT
I H SHIFT 53 I NOS
I VISC CONT 54 I CWZ
I PB O/E 55 I DTV
I CINC 56 I SVV
I CGINC 57 — GND
— GND 58 — V
DD
I MODE 59 I CLR
O W O/E 60 O WV1
O TOT1 61 O WV2
O TOT2 62 I SHW
O XINS 63 I YWZ
I FRB 64 O GSHW
21
YINC
2
40
CINC
1
WCK PB 2H
GEN.
16
PB V
SV V
WRITE V
V
TIMING
DETECT
GEN.
9
SWP
48
SYNC
FRB
49 MIX
RSH
CONTROL
24
READ CONT READ VISC
38
DETECT
VISC CONT
55
DTV
52
DT
36
V SHFT
37
H SIFT
VISC
28
VISC EX ENABLE
8
GEN.
REF O/E
39
PB O/E
23
HCK
22
BIDIREX
RZ
63
DETCT
YWZ
54
CWZ
2
WRITE V
COUNTER COUNTER
1
7
RVD
62
SHW
43
MODE
3-5
DIAG 1-3
TBC MPU I/F
51
YHG
53
NOS
59
CLR
32 31 30
STB SIN SCK
20
MEMORY YGINC
41
2 LINE VONTROL
CGINC
11
PB2H
44
W O/E
2 2 60,61
WV 1, WV 2
13
SYMX
14
PSW
34
FCP
47
X INS
50
SQW
27
NORPB
33
VISC RST
35
VISC DET
19
YBID
12
CBID
17
BIDDIR
18
COUNTER
WRITE V
CNTV
V GEN.
2
64
SYNC
GSHW
GATE
29
SOUT
2-17
IC