Sony BVW-55 Maintenance Manual page 596

IC
CXD8818R (SONY)
C-MOS MEMORY CONTROLLER
—TOP VIEW—
181
185
V L
DD
GND
190
195
V H
DD
GND
200
205
210 GND
215
220
V L
DD
GND
225
230
V H
DD
235 GND
240
PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
1 I M2CF I
49 DID4
M3D9
2 I 50 I DID3
I M3D8 I
3 51 DID2
M3D7
4 I 52 I DID1
I M3D6 I
5 53 DID0
6 — V L 54 — V
DD
GND —
7 — 55 GND
I M3D5 I
8 56 DIHD
M3D4
9 I 57 I DIVD
I M3D3 I
10 58 DIP
M3D2
11 I 59 O CHD
I M3D1 O
12 60 CVD
M3D0
13 I 61 I ISY
M3HD
14 I 62 O HR
I M3VD I
15 63 SFTHR
M3CF
16 I 64 O SMPP
O SAVP O
17 65 PCEN
V
18 — H 66 — V
DD
— —
19 GND 67 GND
20 I I
DED9 68 W27
21 I DED8 69 O DTHP
I O
22 DED7 70 CH
23 I DED6 71 O CLPP
I I
24 DED5 72 A1D9
25 I DED4 73 I A1D8
I
26 I DED3 74 A1D7
27 I I
DED2 75 A1D6
28 I DED1 76 I A1D5
I —
29 DED0 77 V
DD
30 — GND 78 — GND
I I
31 DECCK 79 A1D4
32 I DEHD 80 I A1D3
I
33 I DEVD 81 A1D2
I I
34 DECF 82 A1D1
35 I DEP 83 I A1D0
I I
36 DICPST 84 A1P
37 I DICR 85 O YCER
I O
38 DICF2 86 BCER
39 I DICF1 87 O
RCER
O
40 I DICF0 88 COE
I O
41 DIFCK 89 HFCK
42 — V L 90 — GND
DD
— O
43 GND 91 QTCK
44 I DID9 92 I A2D9
I I
45 DID8 93 A2D8
I 94 I
46 DID7 A2D7
47 I DID6 95 I A2D6
I I
48 DID5 96 A2D5
2-46
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
97 I A2D4 145 O 193
MWC4
I O
98 A2D3 146 MWC3 194
I 147 O 195
99 A2D2 MWC2
100 I A2D1 148 O MWC1 196
— O
101 V L 149 MWC0 197
DD
H 102 — GND 150 — GND 198
DD
I O
103 A2D0 151 MWCK 199
104 I 152 O 200
A2P MWRST
O
105 O IVST 153 MRCK 201
I O 202
106 M1D9 154 MRRST
107 I M1D8 155 I RDY9 203
I I
108 M1D7 156 RDY8 204
109 I M1D6 157 I RDY7 205
I I
110 M1D5 158 RDY6 206
I 159 I 207
111 M1D4 RDY5
I
112 I M1D3 160 RDY4 208
I O 209
113 M1D2 161 WRSTL
L 114 — V H 162 — V L 210
DD DD DD
— —
115 GND 163 GND 211
116 I 164 I 212
M1D1 RDY3
I I
117 M1D0 165 RDY2 213
I 166 I 214
118 M1HD RDY1
I
119 I M1VD 167 RDY0 215
I I 216
120 M1CF 168 RDP
121 O ICF0 169 I RDFIN 217
O I
122 ICF1 170 RDC9 218
123 O 171 I 219
ICF2 RDC8
O I
124 MWY9 172 RDC7 220
O 173 I 221
H 125 MWY8 RDC6
126 — V L 174 — V H 222
DD DD
— —
127 GND 175 GND 223
128 O MWY7 176 I RDC5 224
O I
129 MWY6 177 RDC4 225
130 O 178 I 226
MWY5 RDC3
O I
131 MWY4 179 RDC2 227
O I 228
132 MWY3 180 RDC1
133 O MWY2 181 I RDC0 229
O O
134 MWY1 182 RDRSTL 230
135 O 183 I 231
MWY0 ASTB
O I
136 MWP 184 WR 232
O 185 I 233
137 MWFIN RD
—
138 — V H 186 V L 234
DD DD
— — 235
139 GND 187 GND
140 O MWC9 188 I/O MAD7 236
O I/O
141 MWC8 189 MAD6 237
142 O 190 I/O 238
MWC7 MAD5
O I/O
143 MWC6 191 MAD4 239
O 192 I/O 240
144 MWC5 MAD3
INPUT
A1D0 - 9 ; A/D CONVERTED Y SIGNAL DATA FROM DIGITAL FILTER
A1P ; A/D CONVERTED Y SIGNAL DATA PARITY
A2D0 - 9 ; A/D CONVERTED R-Y/B-Y SIGNAL DATA FROM DIGITAL FILTER
120
A2P ; A/D CONVERTED R-Y/B-Y SIGNAL DATA PARITY
ADVCF ; ADVANCED REFERENCE COLOR FRAME
GND 115 ASTB ; MPU INTERFACE ADDRESS STROBE
V H
DD
DECK ; COMPOSITE DECODER INPUT CLOCK
DECF ; COMPOSITE DECODER INPUT CF
110
DED0 - 9 ; COMPOSITE DECODER INPUT DATA
DEHD ; COMPOSITE DECODER INPUT HD
105
DEP ; COMPOSITE DECODER INPUT PARITY
DEVD ; COMPOSITE DECODER INPUT VD
GND
V L
DD DICF0 - 2 ; DIF (SERIAL DIGITAL) INPUT CF
100
; DIF (SERIAL DIGITAL) INPUT COMPOSITE FLAG (H : COMPOSITE)
DICPST
DICR ; DIF (SERIAL DIGITAL) INPUT CRCC ERROR FLAG (H : ERROR)
95
DID0 - 9 ; DIF (SERIAL DIGITAL) INPUT DATA
DIFCK ; DIF (SERIAL DIGITAL) INPUT CLOCK
DIHD ; DIF (SERIAL DIGITAL) INPUT HD
GND 90
DIP ; DIF (SERIAL DIGITAL) INPUT PARITY
DIVD ; DIF (SERIAL DIGITAL) INPUT VD
85
FNTC ; FORCED NTSC MODE
ISY ; ANALOG COMPONENT SYNC INPUT
; MULTI-LOOP (1) INPUT CF FOR SELF-DIAG.
M1CF
80
M1D0 - 9 ; MULTI-LOOP (1) INPUT DATA FOR SELF-DIAG.
GND
V H
DD
M1HD ; MULTI-LOOP (1) INPUT HD FOR SELF-DIAG.
75
M1VD ; MULTI-LOOP (1) INPUT VD FOR SELF-DIAG.
M2CF ; MULTI-LOOP (2) INPUT CF
M2D0 - 9 ; MULTI-LOOP (2) INPUT DATA
70
M2HD ; MULTI-LOOP (2) INPUT HD
GND
M2VD ; MULTI-LOOP (2) INPUT VD
V L
DD
65
M3CF ; MULTI-LOOP (3) INPUT COLOR FRAME FOR SELF-DIAG.
M3D0 - 9 ; MULTI-LOOP (3) INPUT DATA FOR SELF-DIAG.
61
M3HD ; MULTI-LOOP (3) INPUT HD FOR SELF-DIAG.
M3VD ; MULTI-LOOP (3) INPUT VD FOR SELF-DIAG.
R27 ; REFERENCE 27MHz CLOCK
RD ; MPU INTERFACE READ REQUEST
RDC0 - 9 ; MEMORY READ R-Y/B-Y DATA
RDFIN ; MEMORY READ DATA FINISH BLOCK ID BIT
; MEMORY READ DATA PARITY
RDP
RDY0 - 9 ; MEMORY READ Y DATA
RST ; MASTER RESET
I/O SIGNAL
SFTHR ; SHIFTED HR INPUT
I/O
MAD2
TEST ; TEST MODE ENABLE
I/O
MAD1
W27 ; 27MHz CLOCK LOCKED TO ANALOG COMPONENT
I/O
MAD0
WR ; MPU INTERFACE WRITE REQUEST
O
MPUCK
—
V H OUTPUT
DD
— GND BCER ; B-Y SIGNAL CLAMP ERROR
I
R27 BCF ; BUFFERED CF
I ; BUFFERED DATA
ADVCF BD0 - 9
I
TEST BHD ; BUFFERED HD
O
SRP BP ; BUFFERED PARITY
O
REFCF0 BVD ; BUFFERED VD
O
REFCF1 CH ; COUNT H TIMING PULSE FOR PLL
O REFCF2 CHD ; ANALOG COMPONENT HD OUTPUT
I
FNTC CLPP ; CLAMP PULSE FOR ANALOG COMPONENT
I COE ; ANALOG COMPONENT ODD/EVEN OUTPUT
RST
O
R18 CVD ; ANALOG COMPONENT VD OUTPUT
O DTHP ; DITHER TIMING PULSE FOR A/D DITHER
SUPT
—
GND HFCK ; 13.5MHz CLOCK (W27/2) FOR DIGITAL FILTER
O ; PHASE COMPARATOR PULSE OUT FOR PLL
BD9 HR
O BD8 ICF0 - 2 ; SELECTED INPUT SIGNAL COLOR FRAME
O
BD7 IVST ; SELECTED INPUT SIGNAL V-START PULSE
O MPUCK ; MPU INTERFACE CLOCK (9MHz)
BD6
O
BD5 MRCK ; MEMORY READ CLOCK
O MRRST ; MEMORY READ RESET PULSE
BD4
O BD3 MWC0 - 9 ; MEMORY R-Y/B-Y DATA OUTPUT
O MWCK ; MEMORY WRITE CLOCK
BD2
O MWFIN ; MEMORY WRITE DATA FINISH BLOCK ID BIT
BD1
O MWP ; MEMORY WRITE DATA PARITY OUTPUT
BD0
— MWRST ; MEMORY WRITE RESET PULSE
V L
DD
—
GND MWY0 - 9 ; MEMORY WRITE Y DATA OUTPUT
O PCEN ; PHASE COMPARATE ENABLE
BHD
O BVD QTCK ; 6.75MHz CLOCK (W27/4) FOR DIGITAL FILTER
O R18 ; 18MHz CLOCK OUTPUT FOR PLAYER SELF-DIAG.
BCF
O RCER ; R-Y SIGNAL CLAMP ERROR
BP
I RDRSTL ; MEMORY READ RESET LINE
M2D9
I REFCF0 - 2 ; REFERENCE CF
M2D8
I SAVP ; SELECTED INPUT SIGNAL SAV TIMING PULSE
M2D7
I SMPP ; SAMPLING PULSE FOR PLL
M2D6
SRP ; SERVO REFERENCE PULSE
I
M2D5
I SUPT ; TIMING PULSE FOR SET-UP REMOVER
M2D4
WRSTL ; MEMORY WRITE RESET LINE
I M2D3
— YCER ; Y SIGNAL CLAMP ERROR
V H
DD
— GND
I
M2D2 INPUT/OUTPUT
I MAD0 - 7 ; MPU INTERFACE DATA BUS
M2D1
I
M2D0
I
M2HD
I
M2VD
BVW-55