Toshiba GRL100-701B Instruction Manual page 19

B-MODE, and the latter is applied to GPS-MODE.
The intra-system synchronization keeps the sampling timing error between the terminals within
±10µs or ±20µs and the GPS-based system keeps it within ±5µs or ±10µs for two- or
three-terminal applications.
In both methods, the sampling synchronization is realized through timing synchronization
control and sampling address synchronization control. These controls are performed once every
two power cycles.
2.2.7.1 Intra-system Synchronized Sampling for A-MODE and B-MODE
The synchronized sampling is realized using sampling synchronization control signals
transmitted to other terminals together with the power system data. This synchronized sampling
requires neither an external reference clock nor synchronization of the internal clocks of the
relays at different terminals. The transmission delay of the channel is corrected automatically.
Timing synchronization
One of the terminals is selected as the time reference terminal and set as the master terminal. The
other terminal is set as the slave terminal. The scheme switch [SP.SYN] is used for the settings.
Note: The master and slave terminals are set only for the convenience of the sampling timing
synchronization. The GRL100s at all terminals perform identical protection functions and
operate simultaneously.
To perform timing synchronization for the slave terminal, the sampling time difference between
master and slave terminals is measured. The measurement principle of the sampling time
difference ∆T is indicated in Figure 2.2.7.1. The master terminal and slave terminal perform
their own sampling and send a signal that becomes the timing reference for the other terminal.
Master
terminal
∆T
Slave
terminal
Each terminal measures the time T M and T F from its own sampling instant to the arrival of the
signal from the other terminal. As is evident from the figure, the times T M and T F can be
obtained by equation (1) and (2) where T d1 and T d2 are the transmission delay of the channel in
each direction. The sampling time difference ∆T can be obtained from the resulting equation (3).
T M = T d1 − ∆T
T F = T d2 + ∆T
∆T = {(T F − T M ) + (T d1 − T d2 )}/2
The slave terminal advances or retards its sampling timing based on the time ∆T calculated from
equation (3), thereby reducing the sampling time difference with the master terminal to zero.
This adjustment is performed by varying the interval of the sampling pulse generated by an
T M
T d1
Figure 2.2.7.1 Timing Synchronization
(1)
(2)
(3)
 18 
T d2
T F
6 F 2 S 0 8 5 0
t
Sampling
timing
t