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Scheme Logic
Figures 2.9.2.2 (a) and 2.9.2.3 (a) show the scheme logic of the UVS1 and UVG1 undervoltage
protection with selective definite time or inverse time characteristic.
The definite time protection is selected by setting [UV∗1EN] to "DT", and trip signal
UV∗1_TRIP is given through the delayed pick-up timer TU∗1. The inverse time protection is
selected by setting [UV∗1EN] to "IDMT", and trip signal UV∗1_TRIP is given.
The UVS1 and UVG1 protections can be disabled by the scheme switch [UV∗1EN] or the PLC
signal UV∗1_BLOCK.
These protections are available to trip instantaneously by the PLC signal UV∗1_INST_TP
except for [UV∗1EN]= "OFF" setting.
Figures 2.9.2.2 (b) and 2.9.2.3 (b) shows the scheme logic of the UVS2 and UVG2 protection
with definite time characteristic. The UV∗2 gives the signal UV∗2_ALARM through delayed
pick-up timer TU∗2.
The UV∗2_ALARM can be blocked by incorporated scheme switch [UV∗2EN] and the PLC
signal UV∗2_BLOCK.
These protections are also available to alarm instantaneously by the PLC signal
UV∗2_INST_TP except for [UV∗1EN]= "OFF" setting.
In addition, there is user programmable voltage threshold UVSBLK and UVGBLK. If all three
phase voltages drop below this setting, then both UV∗1 and UV∗2 are prevented from operating.
This function can be blocked by the scheme switch [VBLKEN]. The [VBLKEN] should be set to
Undervoltage Inverse Time
Curves
1000.000
100.000
TMS = 10
10.000
TMS = 5
TMS = 2
TMS = 1
1.000
0
0.2
0.4
0.6
Applied Voltage (x Vs)
Figure 2.9.2.1 IDMT Characteristic
98
6 F 2 S 0 8 5 0
0.8
1
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