Toshiba TLCS-90 Series Data Book page 122

TOSHIBA
Address~--------------~
63
Data Memory
32
f------------
31 Resister Bank 1
24 RE1
2 3 - - - - - - - - - - -
8 Level Stack
8
("16 byte)
7
-R-;;i-;te~ -B~;k--O
o
REO
Internal Data Memory Area
TMP 804 8P I , TMP 80 35P I
• RAM locations 8 - 23 serve a dual role in that they contain the
~rogram
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations stora returning addresses fro=
sub~outines.
If the level of
subroutine nesting 15 less than the permitted 8, you free up 2 bytes of
~~
for general use for every level of nesting not utilized.
• A.:.L
~ 1:)ca::'c:15 a:--e in::irectl;" a:::::re5s.:::e thro-.;;l.... eit::er cf
t ..
c
R..!_'::
Pointer R~gisters
"'-:--.i::'
reside at RO and Rl of the Register array.
• The TX?5048 architecture
allo~s extension of the Data Memory to 256 words.
(3)Input!Output Ports
• The TMP8048 has 27 I/O lines which can be used for either input or output.
These I/O lines are grouped into 3 ports each having 8 bidirectional lines
and 3 "test'; inputs which can alter program sequences when tested by con-
ditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten. As input ports these lines are non-latching, i.e •• inputs
must be present until read by an input instruction.
• All lines of Ports land 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line is
continously pulled to a +5V level through a high impedance resistive device
(SOkn ) which is sufficient to provide the source current for a TTL high
level yet can be pulled low by a standard TTL gate thus allowing the same
p in to be used for both input and output. In order to speed up t he "0"
to "1" transition a low impedance
de~ice
(Sk<2 ) is switched in momentarily
whenever a "1" is written to line. When a "0" is written to line a low
impedance device overcomes the pullup and provides TTL current sinking
capabi 1 i ty.
MCU48-1l2