Toshiba TLCS-90 Series Data Book page 284

TOSHIBA
TMP90C840
Note that the set value of TREGO must be smaller than that of TREGI.
In this mode, the up-counter UCO of Timer 0 is disabled (Set TRUN 0
0, and stop and clear Timer 0).
The PPG mode can be illustrated as follows:
¢Tl
¢T16
TMOD3 , 2 TCLK3, 2
f.
00
=
10
Internal Data Bus
Fig. 3.6 (10) Block Diagram of8-bit PPG Mode
Example: Generate pulse at 50kHz and 1/4 duty rate (@fc
.sL.JL---ILJ
W
t = 1/50
(ms)
o Calculate the set values of the timer registers.
TFFCRl
=
1
8MHz)
To obtain the frequency of 50kHz, the pulse cycle t should be:
1150kHz
=
20lls.
Given oTl
=
Ills (@8MHz),
20lls/ Ills
=
20
Conseq uent ly, the timer register 1 (TREGl) shou ld be set to 20
14H.
Given a 1/4 duty, t x 1/4
=
20 x 1/4
=
5 llS
5 llS / 1 llS
=
5
As a result, the timer register 0 (TREGO) should be set to 5'
=
05H.
MPU90-86