Operation - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.10.3 Operation
The watchdog timer generates INTWD (watchdog timer interrupt) after a
time specified by the register WDMOD6, 5 (WDTP). The binary counter
for the watchdog timer is cleared to "0" by software (instruction)
before the interrupt occurs. If the CPU caused a malfunction
(runaway) for reason such as noise and fails to execute the
instruction to clear the binary counter, the counter will overflow and
the watchdog timer interrupt INTWD occurs. The CPU detects the
malfu~ction
(runaway) by this interrupt.
The watchdog timer starts its operation as soon as the reset state is
cleared.
The watchdog timer stops its operation only in the STOP mode. When
the STOP mode is released, the watchdog timer starts its operation
after a specified warming-up time.
In the other standby mode (IDLE 1, IDLE 2 or RUN modes), the watchdog
timer is enabled. However, the function can be disabled before
selecting any of these modes.
Example: (1) Clear the binary counter.
WDCR
<-
01001110 Write clear code (4ER)
(2) Set 2
16
/fc for the detecting time of watchdog timer.
WDMOD
<-
101---XX
(3) Disable the watchdog timer.
WDMOD
<-
O-----XX Clear WDTE to "0"
WDCR
<-
10110001 Write disable code (BIR)
(4) Select the IDLE 2 mode.
WDMOD
<-
0---11XX Disable WDT and set IDLE 2 mode
WDCR
<-
10110001 Select the standby mode
Execute HALT instruction
(5) Select the STOP mode (Warming-up time: 2
16
/fc)
WDMOD
<-
---101XX Select STOP mode
Execute HALT instruction
Select the standby mode
MPU90-133