Toshiba TLCS-90 Series Data Book page 133

TOSHIBA
TMP 8048P I, TMP 80 35P I
. Figure 6 illustrates the timing of accessing the external data memory
during execution of external program.
(3) Interface with I/O Expander (TMP8243P)
The TMP8048 I/O can be easily expanded using the TMP8243 I/O Expander.
THis device uses only the lower half 4-bits of Port 2 for commuication
with the T~W8048. The TMP8243 contains four 4-bit I/O ports which serve
as extensIons of one chip I/O and are addressed as Ports (4-7). All
cOlTID1unication takes place over the lower half of port 2 (P20 - P23) with
timing provided by an output pulse on the PROG pin. Each transfer consists
of two 4-bit nibbles the first containing the "OP Code" and port
address and the second containing the actual 4-bits of data.
+12V
EA
o~r---------------------------------------------------------
RESET
0\_1 - - -_ _
--!I(f~-~d
I)
~
ALE
DBO- DB7
P20, P2l
--------------~~ ~,
Input of Internal
RJ~ Address
Output of Internal
RO~
Data
Input
of
Inte:-u.al
RO~~ Accress
Input
of
Internal
RO~~
Address
I~FU: of Internal
Ro!-1
Address
Fig.7 Timing of Reading Internal Program Memory
5V
5V 10K
5V
D
5
55 Q
F~
74
T
Q
R
ALE
Fig.8
(a)
Single Step Circuit
MCU48-123