Toshiba TLCS-90 Series Data Book page 152

TOSHIBA
Addressr---------------~
127
Data Hemory
32
f------------
31 Resister Bank 1
24 RBI
23'-----------
8 Level Stack
8
(16 byte)
7
r-R~;i;t-e_; -B~;k-O-·
a
RBO
Internal Data Memory Area
TMP8049PI-6,TMP8039PI-6
•
~~
locations 8 - 23 serve a dual role in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the permitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
• ALL 128 locations are indirectly addressable through either of two
~~
Pointer Registers which reside at RO and Rl of the Register array.
• The TMP8049 architecture allows extension of the Data Memory to 256 words.
(3)Input/Output Ports
· The TMP8049 has 27 I/O lines which can be used for elither input or output.
These I/O lines are grouped into 3 ports each having 8 bidirectional lines
and 3 "test" inputs which can alter program sequences when tested by con-
ditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
until rewritten. As input ports these lines are non-latching, i.e., inputs
must be present until read by an input instruction.
• All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line is
continously pulled to a +5V level through a high impedance resistive device
(50kn ) which is sufficient to provide the source current for a TTL high
level yet can be pulled low by a standard TTL gate thus allowing the same
pin to be used for both input and output. In order to speed up the "0"
to "1" transition a low impedance device (5kn ) is switched in momentarily
whenever a "1" is written to line. When a "0" is written to line a low
impedance device overcomes the pullup and provides TTL current sinking
capability.
MCU48-142