Table of Contents
Advertisement
TOSHIBA
TMP90CB40
7
6
S
4
3
2
I
o
I
I
I
I
I
I
I
I
I CTSE I
I
seCR
IRBB I EVEN I PE IOERRlpERRIFERRI
(FFEAH) I
I
I
I
I
I
1/
R
R/W
I
I
I
I
I
I
I
I
I
R
R
1 _ _
>
R
----->
------->
R/W
I
I
R/W
1 _ _
>
Enable hand-shake function
*
I 0 I Disable (always transmitt-I
I
I able)
I
1---1---------------------------1
I I I Enable
I
Framing error flag
Parity error flag
Overrun error flag
Always
cleared to
"0" when
read out
_______________________ >
Enable parity addition
*
I 0 I Disable
I
1---1---------------------------1
I I I Enable
I
______________________________ >
Add/check even parity
*
I 0 I Odd parity
I
1---1---------------------------1
I
I I Even parity
I
______________________________ >
Rec ei ving da t a bi t
B
(S RB )
(Caution)
Since all error flags are cleared after readout, avoid testing
for only one bit by using a bit-testing instruction.
SCBUF
(FFEBH)
Fig.
3.B
(3)
Serial Channel Control Register
7
6
S
4
3
2
I
0
I
I
ITB7:TB6:TBS:TB4:TB3:TB2:TBI:TBOI
(Transmisison)
I
I
7
6
S
4
3
2
I
0
I
I
I RB 7: RB6: RBS: RB4: RB3: RB2: RBI: RBO I
(Rece iving)
I
I
Fig.
3.B
(4)
Serial Transmission/Receiving Buffer Registers
MPU90-II2
Hide quick links:
Advertisement
Table of Contents
