Stop Mode - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
In the IDLE2 mode, the HALT state is released by an interrupt with the
same timing as in the RUN mode, except the internal operation of the
MCU. In the RUN mode, only the CPU stops executing the current
instruction, and the system clock is supplied to all internal devices.
In the IDLE 2 mode, however, the sys tem clock is suppl ied to only
specific internal I/O devices. As a result, the HALT state in the
IDLE 2 mode requires only a 1/3 of the power consumed in the RUN mode.
In the IDLE 2 mode, the system clock is supplied to the following I/O
devices:
o 8-bit timer
o 16-bit timer
o Serial interface
o Watchdog timer
3.4.4 STOP mode
Fig. 3.4 (4) is a timing chart for releasing the HALT state by
interrupts in the STOP mode.
The STOP mode is selected to stop all internal circuits including the
internal oscillator. In this mode, all pins except special ones are
put in the high-impedance state, independent of the internal operation
of the MCU. Table 3.4 summarizes the state of these pins in the STOP
mode. Note, however, that the pre-halt state can be retained by
setting the internal I/O register DRVE (Drive enable: Bit 0 of memory
address FFD2H) to
"1".
The content of this register is initialized to
"0" by resetting.
When the CPU accepts an interrupt request, the internal oscillator is
restarted immediately. However, to s tabil ize the oscillation, the
system clock starts its output after the time set by the warming up
counter WARM (Warming up: Bit 4 of . memory address FFD2H) ha1tfassed16
A warming-up time of either the clock oscillation time
x
2 or 2
can be set by setting this bit to either "0" or
"1".
This bit is
initialized to "0" by resetting.
MPU90-52