Toshiba TLCS-90 Series Data Book page 211

TOSHIBA TMP90C840
(3) Register indirect addressing mode
In the register indirect addressing mode, the operand is located in a
memory address indicated by a register pair (SC, DE,
ilL,
IX, IY or
SP).
Example: LD A, (HL)
Memory
CPU
I
A 45
1<-1------
1 1
45 2000H
1
I
HL
1
2
0 0
o
1 1
1
"45H"
~n
the memory address 2000H is loaded into Register A.
(4) Index addressing mode
In the index addressing mode, the operand is located in a memory
address specified by adding an 8-bit displacement value in the opcode
to the contents of a specified register pair (IX, IY or SP).
Example: LD A, (SP+2)
Memory
CPU
I
67
1<-1------
- - 1 1
A
67 3002H
1
1
SP
1_3~_O
__ O_O_1 1
--------------------1
"67H" in the memory address 3002H is loaded into Register A. The
displacement value ranges from -128 to +127.
(5) Register index addressing mode
In this mode, the operand is located in a memory address specified by
adding the displacement value of Register A to the contents of
register pair HL.
Exampl e: LD B, (HL+A)
MPU90-13