Toshiba TLCS-90 Series Data Book page 93

TOSHIBA
TMP80 CSOAP /-6, TMP 80 C40AP / -6, TMP80 CSOAF /-6,
TMP80CSOAT,TMP80C40AT
8-BIT SINGLE-CHIP MICROCOMPUTER
TMP80CSOAP /TMP80CSOAP-6
TMP80C40AP /TMP80C40AP-6
TMP80CSOAF/TMP80CSOAF-6
TMP80CSOAT/TMP80C40AT
GENERAL DESCRIPTION
The TMP80CSOA is a single chip microcomputer fabricated in Silicon Gate Q10S
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 2S6 x 8 RAM data memory, 4K x 8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
Tne TMP80CSOA is particularly efficient as a controller. It has extensive bit
TOSHIBAg capability as well as facilities for both binary and BCD arithme-
tic.
The TMP80C40A/-6 is the equivalent of a TMP80CSOA/-6 without ROM program
memory on chip. By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80CSOAP/-6 and TMP80C40AP/-6 are in a standerd Dual Inline Package.
The TMP80CSOAF/-6 is in a 44-pin Flat Package.
The TMP80CSOAT and TMP80C40AT are packaged in the JEDEC standard type 44pin
PLCC (Plastic Leaded Chip Carrier).
FEATURES
• TMP80CSOAP/TMP80C40AP/TMP80CSOAF/
TMP80CSOAT/TMP80C40AT
1.36~s Instruction Cycle Time
O'C to 70'C, SV
±
10%
• TMP 80 CSOAP -6/TMP 80 C40AP -6/TMP 80CSOAF-6
2.S ~s Instruction Cycle Time
-40'C to 8S'C, SV
±
20%
• Software Upward Compatible with
TMP8049AP/TMP80C49AP-6/INTEL's 8049.
• HALT Instruction (Additional Instruction)
• 4K x 8 masked ROM
• 256 x 8 RAM
• 27 I/O lines
• Interval Timer/Event Counter
MCU48-83
• Low Power
lOmA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
10~A Max. in Power Down Mode
(VCC=SV, fXTAL : DC)
• Single Power Supply
• Power Down Mode (Stand-by Mode)
• Halt Mode (Idle Mode)