Toshiba TLCS-90 Series Data Book page 280

TOSHIBA
Example:
TRUN
TMOD
TCLK
TREG1
INTER
IRUN
-
(Note)
TMP90CB40
To generate Timer 1 interrupt every 4.0us at fc=10 MHz, the
registers should be set as follows:
MSB
7 6
5 4 3
<- - - -
-
-
<-
- - 0
<- -
-
0
<-
0 0 1 1 0
<- - - -
<- - -
1
-
-
x:
Don't
LSB
2 1 0
-
0
-
0 x x
1
0 1 0
-
-
1
-
1
-
care
Stop Timer 1, and clear it to "0".
Set the B-bit timer mode.
Select OT1 (O.Bus @fc=10 MHz) as the
input clock.
Set the timer register at 40us/Tl = 50.
Enable INTT
l.
Start Timer 1.
No change
Use the following table for selecting the input clock:
Table 3.6 (1) B-bit timer interrupt cycle and input clock
Interrupt cycle @fc=10 MHz
O.Bus - 204us
l2.Bus - 3.264ms
204.Bus - 52.429ms
Caution for using Timer
2
Resolution
O.Bus
l2.Bus
204.Bus
Input clock
0Tl
~16
¢T256
Interrupts generated by Timer
2
(INTT2) uses the same interrupt mask
flag (INTEL 7) as used for those of the
AID
converter (INTAD). To
select either interrupt, another flag INTEH3 is provided. Setting
this flag to "0" enables interrupts by Timer 2 and disables those by
the
AID
converter.
[2] Generating pulse at 50% duty
The Timer Flip-flop is inverted at specified intervals, and its status
is output to a timer output pin (TOl or T03).
Example: To output pulse from TOI at fc=10 MHz every 4.Bus, the
registers should be set as follows:
This example uses Timer I, but the same operation can be
effected by using Timer O.
TRUN
TMOD
TCLK
TREGI
TFFCR
7 6 543 2 1 0
<- - - - -
0 -
<- -
0 0
x x
<- - -
0 1
<-
0 0 0 0 0 0 1 0
<- -
0 0 1 1
SMMOD
<-
P67CR
<-
TRUN
<-
(Note) x:
- x x 0 1
1
1 - 1 -
Don't care
Stop Timer 1, and clear it to "0".
Set the B-bit timer mode.
Select ~T1 as the input clock.
Set the timer register at
4.8usl¢T1/2=3.
Clear TFF1 to "Oil, and set to invert by
the match signal from Timer 1.
Select P60 as TOI pin.
Select P60 as TOI pin.
Start Timer 1.
No change
MPU90-B2