Toshiba TLCS-90 Series Data Book page 161

TOSHIBA
XTAU
Input
(6HHz)
H
(2HHz)
-enerated
nternally ¢,2
State
ALE
(400kHz)
P20 - P23
DBO -
DB7
ALE
PSEN
~
1
Instruction
Fetch
1
State
2
Decode
3
Execution
1 Cycle
Fig.4 Instruction Cycle Timing
Address
I
\
!
I
nIT'
80.49PI-6. H1F8039PI- 6
4
Execution
5
Execution
1
L
~ext Address Latch Timing
Address
Address
Instruction
I
\
II
L
Fig. 5
Timing of External Program Memory Access
MCU48-1S1