Toshiba TLCS-90 Series Data Book page 160

TOSHIBA
TMP8049PI-6, T~1P8039PI-6
(1) Instruction Cycle
• The instructions of TMP8049 are executed in one or two machine cycles,
and one machine cycle contents of five states.
Fig.4 illustrates its relationship with the clock input to CPU.
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clock shown in Fig.4 is derived to outside by ENTO
eLK
instruction.
• ALE can be also used as the clock to indicate the machine cycle as well
as giving the external address latch timing.
(2) External Memory Access Timing
(i) Program Memory Access
• TMP8049 programs are excuted 1n the following three modes.
(1)
Execution of internal program only.
(2) Execution of both external and internal programs.
(3)
Execution' of external program only.
The external program memory is accessed (instructions are fetched)
automatically when the internal ROM address is exceeded in mode
(2)
and from initial start address 0 in mode (3).
• In the external program memory access operation, the following will occur
• The contents of the l2-bit program counter will be output on BUS(DBO -
DB7) and the lower 4-bits of Port 2.
• Address Latch Enable (ALE) will indicate the time at which address is
valid. The trailing edge of ALE is used to latch the address
externa lly •
Program Store Enable (PSEN) indicates that an external instruction
fetch is in progress and serves to enable the external memory device.
BUS (DBO - DB7) reverts to Input mode and the processor accepts its
8-bit contents as an Instruction Word.
• Figure 5 illustrates the timing.
(ii) Access of External Data Memory
• In the extended data memory access operation during READ/WRITE cycle the
following occurs
• The contents of RO Rl is output onto BUS (DBO - DB7).
• ALE indciates address is valid. The trailing edge of ALE is used to
latch the address externally.
• A read RD or write WR pulse on the corresponding output pins indicates
the type of data memory access in progress. Output data valid at trail-
ing edge of WR and input data must be valid at trailing edge of
RD.
Data (8-bits) is transferred over BUS.
MCU48-1S0