Micro Dma Processing - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
Table 3.3 (1) lists the possible interrupt sources.
Table 3.3 (1) Interrupt Sources
I I
IPriorityl
I Start ad-I Start ad-
IVectorldress of Idress of
Ivalue Igeneral IMico DMA order Type Interrupt source
1
2
3
4
5
6
7
7
8
9
10
11
12
13
14
Non SWI instruction
maskablelNMI(Input from NMI pin)
I INTWD (watchdog)
I INTO (Externa 1 input 0)
I INTTO (Timer 0)
I INTTI (Timer 1)
I INTT2 (Timer 2)
I INTAD (AID
Converter)
Maskablel INTT3 (Timer 3)
I INTT4 (Timer 4)
I INTI (Externa 1 input
1)
I INTT5 (Timer 5)
I INT2 (External input 2)
I INTRX (End of serial
I
receiving)
I INTTX (End of serial
I
transmission)
I I purpose Iprocessingl
I I interrupt I parameter I
I I process- I I
I I ing I I
I 10H I 001 OH I I
I 18H I 0018H I I
I 20H I 0020H I I
I 28H I 0028H I FF28H I
I 30H I 0030H I FF30H I
I 38H I 0038H I FF38H I
I 40H I 0040H I FF40H I
I 40H I 0040H I FF40H I
I 48H I 0048H I FF48H I
I 50H I 0050H I FF50H I
I 58H I 0058H I FF58H I
I 60H I 0060H I FF60H I
I 68H I 0068H I FF68H I
I 70H I 0070H I FF70H I
I I I I
I 78H I 0078H I FF78H I
I I I
i
(Note) Either INTT2 or INTAD is selected by software.
The "priority order" in the table is the order of the interrupt source
used by the CPU for accepting more than one interrupt requested at one
time.
If interrupt of fourth and fifth orders are requested simultaneously,
for example, an interrupt of the "5th" priority is acknowledged after
a "4th" priority interrupt processing has been completed by a RETI
instruction. However, a lower priority interrupt can be acknowledged
immediately by executing an EI instruction in a program that processes
a higher priority interrupt.
The internal interrupt controller merely determines the priority of
the sources of interrupts to be acknowledged by the CPU when more than
one interrupt are requested at a time. It is, therefore, unable to
compare the priori ty of interrupt be ing executed with the one be ing
requested.
3.3.2 Micro DMA processing
Fig. 3.3 (3) is a flowchart of the micro DMA processing. Parameters
(addresses of source and destination, and transfer mode) for the data
transfer between memories are loaded by the CPU from an address
modified by an interrupt vector value. After the data transfer
between memories accroding to these parameter, these parameters are
MPU90-39