Toshiba TLCS-90 Series Data Book page 69

TOSHIBA
TMP80C49AP /-6, TMP80C39AP /-6, TMP80 C49AF /-6,
TMP80C49AT,TMP80C39AT
8-BIT SINGLE-CHIP MICROCOMPUTER
TMP80C49AP /TMP80C49AP-6
TMP80C39AP /TMP80C39AP-6
TMP80C49AF/TMP80C49AF-6
TMP80C49AT/TMP80C39AT
GENERAL DESCRIPTION
The TMP80C49A is a single chip microcomputer fabricated in Silicon Gate CMOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included
in a single chip; an 8-bit CPU, 128 x 8 RAM data memory, 2K
x
8 ROM program
memory, 27 I/O lines and an 8-bit timer/event counter.
The TMP80C49A is particularly efficient as a controller. It has extensive bit
handling capability as well as facilities for both binary and BCD arithme-
tic.
The TMP80C39A/-6 is the equivalent of a TMP80C49A/-6 without ROM program
memory on chip. By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C49AP/-6 and TMP80C39AP/-6 are in a standard Dual Inline Package.
The TMP80C49AF/-6 is in a 44-pin Flat Package.
The TMP80C49AT and TMP80C39AT are packaged in the JEDEC standard type 44pin
PLCC (Plastic leaded Chip Carrier).
FEATURES
• TMP80C49AP/TMP80C39AP/TMP80C49AF/
TMP80C49AT/TMP80C39AT
1.36~s Instruction Cycle Time
O'C to 70'C, SV
±
10%
• TMP80 C49AP-6/TMP80C39AP -6/TMP80C49AF-6
2.S
~s
Instruction Cycle Time
-40'C to 8S'C, SV
±
20%
• Software Upward Compatible with
TMP8049AP/TMP80C49P-6/INTEL's 8049
• HALT Instruction (Additional Instruction)
• 2K x 8 masked ROM
• 128 x 8 RAM
• 27 I/O lines
• Interval Timer/Event Counter
MCU48-59
• Low Power
lOrnA MAX. in Normal Operation
(VCC=SV, fXTAL=6MHz)
10~A Max. in Power Down
(VCC=SV, fXTAL: DC)
• Single Power Supply
• Power Down Mode (Stand-by Mode)
• Halt Mode (Idle Mode)