Operation; Cpu; Memory Map - Toshiba TLCS-90 Series Data Book

TOSHIBA
TMP90C840
3 • OPERAT ION
This chapter describes the functions and the basic operations of the
TMP90C840 in every block.
3.1 CPU
The TMP90C840 incorporates a high-per formance 8-bi t CPU. This CPU
improve~
its speed of processing, addressing and executing instructions
compared to the conventional 8-bit versions.
This section describes the CPU functions available to the programmer.
3.1.1 Memory map
The TMP90C840 supports a program memory of up to 64K bytes and a data
memory of maximum 1M bytes.
The program memory may be assigned to the address space from OOOOOH to
OFFFFH, while the data memory can be allocated to any address from
OOOOOH to FFFFFH.
(1) Internal ROM
The TMP90C840 internally contains an 8K-byte ROM. The address space
from OOOOH to lFFFH is provided to the ROM. The CPU starts executing
a program from OOOOH by resetting.
The addresses OOlOH to 007FH in this internal ROM area are used for
the entry area for the interrupt processing.
(2) Internal RAM
The TMP90C840 also contains a 256 byte RAM, which is allocated to the
address space from FECOH to FFBFH. The CPU allows the access to a
certain RAM area (FFOOH to FFBFH, 192 bytes) by a short operation code
(opcode) in a "direct addressing mode".
The addresses from FFlOH to FF7FH in this RAM area can be used as
parameter area for micro DMA processing (and for any other purposes
when the micro DMA function is not used).
(3) Internal I/O
The TMP90C840 provides a 48-byte address space as an internal I/O
area, whose addresses range from FFCOH to FFEFH. This I/O area can be
accessed by the CPU using a short opcode in the "direct addressing
mode".
Fig. 3.1 (1) is a memory map indicating the areas accessible by the CPU
in the respective addressing mode.
MPU90-8