Table 5-27. Logical Input Definition Table (8 Registers - 127 Elements) - ABB TPU2000 Technical Manual

Modbus/modbus plus/ modbus tcp/ip automation
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Address
Bit 10 = LOADA
Bit 9 = OCA –1
Bit 8 = OCA-2
Bit 7 = HLDA-1
Bit 6 = LLDA-1
Bit 5 = HLDA-2
Bit 4 = LLDA-2
Bit 3 = HPFA
Bit 2 = LPFA
Bit 1 = VarDA
Bit 0 = PVarA
41159
Logical Output
Bit 15 = NvarA
Bit 14 = PWATT1
Bit 13 = PWATT2
Bit 12 = Reserved
Bit 11 = Reserved
Bit 10 = Reserved
Bit 9 = Reserved
Bit 8 = Reserved
Bit 7 = Reserved
Bit 6 = Reserved
Bit 5 = Reserved
Bit 4 = Reserved
Bit 3 = Reserved
Bit 2 = Reserved
Bit 1 = Reserved
Bit 0 = Reserved
41160
Logical Output
Bit 15 = Reserved
Bit 14 = Reserved
Bit 13 = Reserved
Bit 12 = Reserved
Bit 11 = Reserved
Bit 10 = Reserved
Bit 9 = Reserved
Bit 8 = Reserved
Bit 7 = Reserved
Bit 6 = Reserved
Bit 5 = Reserved
Bit 4 = Reserved
Bit 3 = Reserved
Bit 2 = Reserved
Bit 1 = Reserved
Bit 0 = Reserved
NOTE 1: Drop Out Time is 3 cycles for Alarm Signals. The alarms activate with each operation or power-up
until the counters are reset. The counter alarms are reset when the targets are reset.
NOTE 2: Two Winding Relay Only
NOTE 3: Three Winding Relay Only
(L): This signal is latched and is only reset upon a protocol control command (Section 5), WinECP, ECP, or
Front Panel Interface reset sequence.
Table 5-27. Logical Input Definition Table (8 Registers – 127 Elements)
Register
Address
41161
Logical Input
TPU2000/2000R Modbus/Modbus Plus Automation Guide
Item
Load Current Alarm
Winding 1 Overcurrent Alarm
Winding 2 Overcurrent Alarm
Winding 1 High Level Detector Alarm
Winding 1 Low Level Detector Alarm
Winding 1 High Level Detector Alarm
Winding 2 Low Level Detector Alarm
High Power Factor Alarm
Low Power Factor Alarm
3 Phase kVar Demand Alarm
Positive 3 Phase Power Factor Alarm(lsb rightmost bit)
Unsigned Integer 16 Bits
Negative 3 Phase Kvar Alarm(msb leftmost bit)
Pwinding 1 Positive 3Phase kWatt Alarm
Pwinding 2 Positive 3Phase kWatt Alarm
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved (lsb rightmost bit)
Unsigned Integer 16 Bits
(msb leftmost bit)
(lsb rightmost bit)
Item
Unsigned Integer 16 Bit
Description
Description
107

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