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R
D
TMP91C824
* In case of 16-bit bus memory
TMP91C824
Control signals
D [0:15]
A0
A1
A2
:
:
A16
* In case of 16-bit bus memory, address connection is ... : CPU A1
* In case of 8-bit bus memory, address connection is ... : CPU A0
CS0
CS1
Data
Address
, (
,
: SRAM)
WR
HWR
CS2
EA24, EA25
CS3
Memory
Control signals
D [0:15]
Open
A0
A1
A15
Figure 3.8.3 H/W Setting Example
91C824-116
Data/Stack RAM
CS0
SRAM
000000H to 1FFFFFH (Logical)
8 Mbytes
000000H to 7FFFFFH (Physical)
8 bits
Optional ROM
CS1
FLASH
400000H to 7FFFFFH (Logical)
16 Mbytes
000000H to FFFFFFH (Physical)
16 bits
Program ROM
MROM
CS2
16 Mbytes
C00000H to FFFFFFH (Logical)
16 bits
000000H to FFFFFFH (Physical)
MROM
Data ROM
64 Mbytes
CS3
16 bits
800000H to BFFFFFH (Logical)
0000000H to 3FFFFFFH (Physical)
* In case of 8-bit bus memory
TMP91C824
Control signals
D [0:7]
A0
A1
A2
:
:
A7
=
=
Memory A0, CPU A2
Memory A1...
=
=
Memory A0, CPU A1
Memory A1...
TMP91C824
Memory
Control signals
D [0:7]
A0
A1
A2
A7
2008-02-20
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