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3.3.1
Block Diagram of System Clock
SYSCR0
<XTEN, RXTEN>
XT1
Low-frequency
fs
oscillator
XT2
SYSCR0
<XEN, RXEN>
Clock doubler
X1
High-frequency
oscillator
X2
f
OSCH
f
SYS
φT0
φT
fs
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
DFMCR0<ACT1:0, DLUPTM>
Warm-up timer (High-/low-frequency
oscillator), Lockup timer (DFM)
fc
fc/2
= f
× 4
f
DFM
OSCH
fc/4
Selector
(DFM)
÷2
÷4
Clock gear
DFMCR0<ACT1:0>
TMRA0 to TMRA3
Prescaler
SIO0 to SIO1
Prescaler
SBI
RTC
MLD/ALM
Figure 3.3.2 Block Diagram of System Clock
91C824-14
SYSCR0
<PRCK1:0>
fc/16
f
FPH
÷2
fc/8
SYSCR1<SYSCK>
fc/16
÷8
÷16
SYSCR1<GEAR2, 0>
CPU
RAM
Interrupt
controller
ADC
WDT
I/O ports
CS/WAIT
Controller
TMP91C824
φT
φT0
÷2 ÷4
fs
f
SYS
2008-02-20
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