Toshiba TLCS-900/L1 Series Manual page 34

(3) Operation
a. IDLE2 mode
In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2
setting register, can take place. Instruction execution by the CPU stops.
Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode
halt state by an interrupt.
X1
A0 to A23
D0 to D15
RD
WR
Interrupt for
release
Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
b. IDLE1 mode
In IDLE1 mode, only the internal oscillator and the RTC, MLD continue to operate.
The system clock in the MCU stops. The pin status in the IDLE1 mode is depended on
setting the register SYSCR2<SELDRV, DRVE>. Table 3.3.6, Table 3.3.7 summarizes
the state of these pins in the IDLE mode1.
In the halt state, the interrupt request is sampled asynchronously with the system
clock; however, clearance of the halt state (e.g., restart of operation) is synchronous
with it.
Figure 3.3.7 illustrates the timing for clearance of the IDLE1 mode halt state by an
interrupt.
X1
A0 to A23
D0 to D15
RD
WR
Interrupt
for release
Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
Data
IDLE2
mode
Data
IDLE1 mode
91C824-32
TMP91C824
Data
Data
2008-02-20