Toshiba TLCS-900/L1 Series Manual page 89

(3) Wait control
Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2>) of a chip
select/wait control register specify the number of waits that are to be inserted when
the corresponding memory area is accessed.
The following types of wait operation can be specified using these bits. Bit settings
other than those listed in the table should not be made.
<BxW2:0> Number of Waits
000 2
001 1
(1 + N)
010
011 0
100 Reserved
101 3
110 4
111 8
A reset sets these bits to 000 (2 waits).
(4) Bus width and wait control for an area other than CS0 to CS3
The chip select/wait control register BEXCS controls the bus width and number of
waits when memory locations which are not in one of the four user-specified address
areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for
areas other than CS0 to CS3.
(5) Selecting 16-Mbyte area/specified address area
Setting B2CS<B2M> (Bit 6 of the chip select/wait control register for CS2) to 0
designates the 16-Mbyte area 000FE0H to 000FFFH, 003000H to FFFFFFH as the
CS2 area. Setting B2CS<B2M> to 1 designates the address area specified by the start
address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if
B2CS<B2M> = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are).
A reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area.
Table 3.6.3 Wait Operation Settings
Inserts a wait of 2 states, irrespective of the
Inserts a wait of 1 state, irrespective of the
Samples the state of the
the pin is low, the waits continue and the bus cycle is extended
WAIT
until the pin goes high.
Ends the bus cycle without a wait, regardless of the
Invalid setting
Inserts a wait of 3 states, irrespective of the
Inserts a wait of 4 states, irrespective of the
Inserts a wait of 8 states, irrespective of the
91C824-87
Wait Operation
pin state.
WAIT
pin state.
WAIT
pin after inserting a wait of 1 state. If
WAIT
WAIT
pin state.
WAIT
pin state.
WAIT
pin state.
WAIT
TMP91C824
pin state.
2008-02-20