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Table 3.5.2 I/O Registers and Specifications (1/2)
Port
Pin Name
Port 1
P10 to P17
Input port
(Note 1)
Output port
D8 to D15 bus
Port 2
P20 to P27
Output port
A16 to A23 output
Port 5
P54 to P56
Input port (without PU)
Input port (with PU)
Output port
P54
P55
P56
Port 6
P60 to P64
Output port
P60
P61
P62
P63
P64
EA24 output
P65
EA25 output
P66
P67
Port 7
P70 to P72
Input port (without PU)
Input port (with PU)
Output port
P70
SCK input
SCK output
OPTRX0 input
P71
SDA input
SDA output
SO output
OPTTX0 output
P72
SI input
SCL input
SCL output
X: Don't care
Specification
input (without PU)
BUSRQ
input (with PU)
BUSRQ
output
BUSAK
input (without PU)
WAIT
input (with PU)
WAIT
output
CS
0
output
CS
1
output
CS
2
output
CS
2
A
output
CS
3
output
CS
2
B
output
CS
2
C
output
CS
2
D
output
CS
2
E
(Note 2)
(Note 3)
(Note 2)
(Note 3)
91C824-53
TMP91C824
I/O Register
Pn
PnCR
PnFC PnFC2
X
0
None
X
1
X
X
X
0
None
X
1
0
0
0
None
1
0
0
X
1
0
0
0
1
1
0
1
X
1
1
0
0
None
1
0
X
0
X
1
None
X
1
X
1
X
X
X
1
None
None
X
1
X
X
X
1
X
X
X
0
X
0
0
0
0
1
0
0
X
1
0
X
0
0
X
1
1
1
0
X
X
0
0
X
1
1
X
1
1
1
1
X
X
0
0
X
0
0
X
1
1
2008-02-20
0
0
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
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