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(when baud rate generator Is used and BR0CR<BR0ADDE> = 0)
Frequency Divider
fc [MHz]
(set to BR1CR<BR1S3:0>)
9.830400
↑
↑
↑
12.288000
↑
14.745600
↑
↑
↑
19.6608
↑
↑
↑
↑
22.1184
24.576
↑
↑
↑
↑
↑
↑
27.0336
29.4912
↑
↑
↑
↑
↑
↑
↑
31.9488
Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above.
Note 2: The values in this table are calculated for when fc is selected as the system clock, the clock
gear is set for fc/1 and the system clock is the prescaler clock input f
Timer out clock (TA0TRG) can be used for source clock of UART mode only.
Calculation method the frequency of TA0TRG
Frequency of TA0TRG =
Note 1:The TMRA0 match detects signal cannot be used as the transfer clock in I/O interface mode.
Table 3.9.3 Transfer Rate Selection
Input Clock
φT0
2
76.800
4
38.400
8
19.200
0
9.600
5
38.400
A
19.200
2
115.200
3
76.800
6
38.400
C
19.200
1
307.200
2
153.600
4
76.800
8
38.400
10
19.200
3
115.200
1
384.000
2
192.000
4
96.000
5
76.800
8
48.000
A
38.400
10
24.000
B
38.400
1
460.800
3
153.600
4
115.200
6
76.800
9
51.200
C
38.400
F
30.720
10
28.800
D
38.400
Baud rate × 16
91C824-128
TMP91C824
Unit (kbps)
φT2
φT8
φT32
19.200
4.800
1.200
9.600
2.400
0.600
4.800
1.200
0.300
2.400
0.600
0.150
9.600
2.400
0.600
4.800
1.200
0.300
28.800
7.200
1.800
19.200
4.800
1.200
9.600
2.400
0.600
4.800
1.200
0.300
76.800
19.200
4.800
38.400
9.600
2.400
19.200
4.800
1.200
9.600
2.400
0.600
4.800
1.200
0.300
28.800
7.200
1.800
96.000
24.000
6.000
48.000
12.000
3.000
24.000
6.000
1.500
19.200
4.800
1.200
12.000
3.000
0.750
9.600
2.400
0.600
6.000
1.500
0.375
9.600
2.400
0.600
115.200
28.800
7.200
38.400
9.600
2.400
28.800
7.200
1.800
19.200
4.800
1.200
12.800
3.200
0.800
9.600
2.400
0.600
7.680
1.920
0.480
7.200
1.800
0.450
9.600
2.400
0.600
.
FPH
2008-02-20
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