Toshiba TLCS-900/L1 Series Manual page 199

3.12.3 Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared 0 by software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be
generated. The CPU will detect malfunction (Runaway) due to the INTWD interrupt and
in this case it is possible to return to the CPU to normal operation by means of an anti-
malfunction program.
The watchdog timer works immediately after reset.
The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter
continues counting during bus release (when
When the device is in IDLE2 mode, the operation of WDT depends on the
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
Example:
a. Clear the binary counter.
WDCR
b. Set the watchdog timer detection time to 2
WDMOD ← 1 0 1 X X – – –
c. Disable the watchdog timer.
WDMOD ← 0 – – X X – – –
WDCR
← 0 1 0 0 1 1 1 0
Write the clear code (4EH).
Clear WDTE to 0.
← 1 0 1 1 0 0 0 1
Write disable code (B1H).
91C824-197
goes low).
BUSAK
/f .
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SYS
TMP91C824
2008-02-20