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(8) UART/serial channel (1/2)
(8-1) UART/SIO channel 0
Symbol
Name
Address
Serial
200H
SC0BUF
channel 0
(Prohibit
buffer
RMW)
Serial
SC0CR
channel 0
201H
control
Serial
SC0MOD0
channel 0
202H
mode0
Baud rate
BR0CR
203H
control
Serial
channel 0
BR0ADD
204H
K setting
register
Serial
SC0MOD1
channel 0
205H
mode1
(8-2) IrDA
Symbol
Name
Address
IrDA
SIRCR
control
207H
register
7
6
5
RB7/TB7
RB6/TB6
RB5/TB5
R (Receiving)/W (Transmission)
RB8
EVEN
PE
R
R/W
Undefined
0
0
Receiving
Parity
1: Parity
data bit8
0: Odd
Enable
1: Even
TB8
CTSE
RXE
0
0
0
1: CTS
1: Receive
Transmission
enable
enable
data bit8
−
BR0ADDE BR0CK1
0
0
00: φT0
1: (16 − K)/16
Always
01: φT2
write 0
divided
10: φT8
11: φT32
I2S0
FDPX0
R/W
R/W
0
0
IDLE2
Duplex
0: Stop
0: Half
1: Operate
1: Full
7
6
5
PLSEL
RXSEL
TXEN
R/W
R/W
R/W
0
0
0
Receiving
Transmission
Transmission
data
0: Disable
pulse width
0: 3/16
0: H pulse
1: Enable
1: 1/16
1: L pulse
91C824-248
4
3
2
RB4/TB4
RB3/TB3
RB2/TB2
Undefined
OERR
PERR
FERR
R (Cleared to 0 by reading)
0
0
0
1: Error
Overrun
Parity
Framing
WU
SM1
SM0
R/W
0
0
0
1: Wakeup
00: I/O interface
enable
01: UART 7 bits
10: UART 8 bits
11: UART 9 bits
BR0CK0
BR0S3
BR0S2
R/W
0
0
0
Setting the divided frequency "N"
BR0K3
BR0K2
0
0
Sets the frequency divisor "K"
(Divided by N + (16 − K)/16)
4
3
2
RXEN
SIRWD3
SIRWD2
R/W
0
0
0
Receiving
Set the effective SIRRxD pulse width
Pulse width more than 2x × (Set value + 1) +
0: Disable
1: Enable
100ns
Possible: 1 to 14
Not possible: 0, 15
TMP91C824
1
0
RB1/TB1
RB0/TB0
SCLKS
IOC
R/W
0
0
0: SCLK0↑
1: Input
1: SCLK0↓
SCLK0
SC1
SC0
0
0
00: TA0TRG
01: Baud rate
10: Internal clock f
SYS
11: External clock
BR0S1
BR0S0
0
0
(0 to F)
BR0K1
BR0K0
R/W
0
0
1
0
SIRWD1
SIRWD0
R/W
0
0
2008-02-20
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