Toshiba TLCS-900/L1 Series Manual page 96

(3) Timer registers (TA0REG and TA1REG)
These are 8-bit registers which can be used to set a time interval. When the value
set in the timer register TA0REG or TA1REG matches the value in the corresponding
up counter, the comparator match detect signal goes active. If the value set in the
timer register is 00H, the signal goes active when the up counter overflows.
The TA0REG are double buffer structure, each of which makes a pair with register
buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG's double
buffer structure is enabled or disabled. It is disabled if <TA0RDE> = 0 and enabled if
<TA0RDE> = 1.
When the double buffer is enabled, data is transferred from the register buffer to
the timer register when a 2
cycle in PPG mode. Hence the double buffer cannot be used in timer mode.
A reset initializes <TA0RDE> to 0, disabling the double buffer. To use the double
buffer, write data to the timer register, set <TA0RDE> to 1, and write the following
data to the register buffer. Figure 3.7.3 show the configuration of TA0REG.
Timer registers 0 (TA0REG)
Shift trigger
Register buffers 0
Write
Internal data bus
Figure 3.7.3 Configuration of TA0REG
Note: The same memory address is allocated to the timer register and the register buffer.
When <TA0RDE> = 0, the same value is written to the register buffer and the timer
register; when <TA0RDE> = 1, only the register buffer is written to.
The address of each timer register is as follows.
TA0REG: 000102H
TA2REG: 00010AH
All these registers are write only and cannot be read.
overflow occurs in PWM mode, or at the start of the PPG
n
B
Y
Selector
A
S
TA01RUN<TA0RDE>
TA1REG: 000103H
TA3REG: 00010BH
91C824-94
TMP91C824
Matching detection in PPG cycle
n
2 overflow of PWM
Write to TA0REG
2008-02-20