Toshiba TLCS-900/L1 Series Manual page 88

(1) Master enable bits
Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the
master bit which is used to enable or disable settings for the corresponding address
area. Writing 1 to this bit enables the settings. Reset disables (Sets to 0) <B0E>,
<B1E> and <B3E>, and enabled (Sets to 1) <B2E>. This enables area CS2 only.
(2) Data bus width selection
Bit 3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip
select/wait control register specifies the width of the data bus. This bit should be set
to 0 when memory is to be accessed using a 16-bit data bus and to 1 when an 8-bit
data bus is to be used.
This process of changing the data bus width according to the address being
accessed is known as dynamic bus sizing. For details of this bus operation see Table
3.6.2.
Operand Data Operand Start
Bus Width Address
2n + 0
8 bits
(Even number)
2n + 1
(Odd number)
2n + 0
16 bits
(Even number)
2n + 1
(Odd number)
2n + 0
32 bits
(Even number)
2n + 1
(Odd number)
Note: xxxxx indicates that the input data from these bits are ignored during a read. During a write,
indicates that the bus for these bits goes too high impedance; also, that the write strobe signal
for the bus remains inactive.
Table 3.6.2 Dynamic Bus Sizing
Memory Data
CPU Address
Bus Width
2n + 0
8 bits
2n + 0
16 bits
2n + 1
8 bits
2n + 1
16 bits
2n + 0
8 bits
2n + 1
2n + 0
16 bits
2n + 1
8 bits
2n + 2
2n + 1
16 bits
2n + 2
2n + 0
8 bits
2n + 1
2n + 2
2n + 3
2n + 0
16 bits
2n + 2
2n + 1
8 bits
2n + 2
2n + 3
2n + 4
2n + 1
16 bits
2n + 2
2n + 4
91C824-86
TMP91C824
CPU Data
D15 to D8 D7 to D0
xxxxx b7 to b0
xxxxx b7 to b0
xxxxx b7 to b0
b7 to b0 xxxxx
xxxxx b7 to b0
xxxxx b15 to b8
b15 to b8 b7 to b0
xxxxx b7 to b0
xxxxx b15 to b8
b7 to b0 xxxxx
xxxxx b15 to b8
xxxxx b7 to b0
xxxxx b15 to b8
xxxxx b23 to b16
xxxxx b31 to b24
b15 to b8 b7 to b0
b31 to b24 b23 to b16
xxxxx b7 to b0
xxxxx b15 to b8
xxxxx b23 to b16
xxxxx b31 to b24
b7 to b0 xxxxx
b23 to b16 b15 to b8
xxxxx b31 to b24
2008-02-20