Read Cycle - Toshiba TLCS-900/L1 Series Manual

(3) Read cycle

f
FPH
EA24, EA25,
A23 to A0
CSn
R/
W
WAIT
Port input
(Note)
RD
D0 to D15
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as and
RD
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local Toshiba
sales representative.
t
FPH
t
AW
t
AP
t
APH2
t
AD
t
AC
t
RD
are not enabled. Therefore, the above waveform diagram should be
CS
91C824-224
t
CW
t
CAR
t
RR
t
HR
D0 to D15
TMP91C824
2008-02-20