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4.9
Bus Request/Bus Acknowledge
BUSRQ
BUSAK
AD0 to AD15
A0 to A23,
,
RD
WR
to
,
CS0
CS3
R/
,
W
HWR
ALE
Symbol
Parameter
Output buffer off to
t
ABA
high to output buffer on
BUSAK
t
BAA
Note 1: Even if the
BUSRQ
The bus will only be released when
Note 2: This line shows only that the output buffer is in the off state.
It does not indicate that the signal level is fixed.
Just after the bus is released, the signal level set before the bus was released is maintained
dynamically by the external capacitance. Therefore, to fix the signal level using an external
resister during bus release, careful design is necessary, since fixing of the level is delayed.
The internal programmable pull-up/pull-down resistor is switched between the active and non-
active states by the internal signal.
(Note 1)
t
CBAL
t
ABA
Variable
Min
Max
low
BUSAK
0
0
signal goes low, the bus will not be released while the
BUSRQ
91C824-229
(Note 2)
(Note 2)
= 4 MHz
f
f
FPH
FPH
Min
Max
Min
80
0
80
0
80
0
80
0
goes low while
is high.
WAIT
TMP91C824
t
BAA
= 16 MHz
Unit
Max
80
ns
80
ns
signal is low.
WAIT
2008-02-20
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